this has to be almost entirely rewritten
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@ -14,9 +14,9 @@ section you need without having to read the entire thing.
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## Organization of the Project
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Upsilon uses LiteX and ZephyrOS for it's FPGA code. LiteX generates HDL
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Upsilon uses LiteX and Linux for it's FPGA code. LiteX generates HDL
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and glues it together. It also forms the build system of the hardware
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portion of Upsilon. ZephyrOS is the kernel portion, which deals with
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portion of Upsilon. Linux is the kernel portion, which deals with
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communication between the computer that receives scan data and the
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hardware that is executing the scan.
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@ -34,9 +34,8 @@ to write much of it.
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The kernel is written in C. This C is different than C you have written
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before because it is running "freestanding."
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The kernel uses Zephyr as the real-time operating system running the
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code. Zephyr has very good documentation and a very readable code base,
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go read it.
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You do not need to know about Linux kernel development. You will need
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to know the basics of ssh, vi, and how to use Unix as a user.
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Tests are written in C++ and verilog. You will not have to write C++
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unless you modify the Verilog files.
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@ -45,12 +44,10 @@ The macro processing language GNU m4 is used occasionally. You will
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need to know how to use m4 if you modify the main `base.v.m4` file
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(e.g. adding more software-accessable ports).
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Python is used for the bytecode assembler, the bytecode itself, and
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the SoC generator. The SoC generator uses a library called LiteX,
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which in turn uses migen.
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You do not need to know a lot about migen, but LiteX's documentation
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is poor so you will need to know some migen in order to read the
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code and understand how some modules work.
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Python is used the SoC generator. The SoC generator uses a library called
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LiteX, which in turn uses migen. You do not need to know a lot about migen,
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but LiteX's documentation is poor so you will need to know some migen in order
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to read the code and understand how some modules work.
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# Compile Process
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@ -81,29 +78,6 @@ compile things on any computer with an internet connection.
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All commands should be done in the conda environment.
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### Zephyr OS
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These instructions are based on [these][zephyr_getting_started], but the Zephyr
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environment should be installed into the F4PGA conda environment,
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[zephyr_getting_started]: https://docs.zephyrproject.org/latest/develop/getting_started/index.html
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1. Run `pip3 install west`
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2. Run
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```
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west init $ZEPHYR_DIRECTORY/zephyrproject
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cd $ZEPHYR_DIRECTORY/zephyrproject
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west update
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west zephyr-export
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pip install -r ~/zephyrproject/zephyr/scripts/requirements.txt
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cd $ZEPHYR_DIRECTORY/zephyrproject
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wget https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.16.0/zephyr-sdk-0.16.0_linux-x86_64.tar.xz
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wget -O - https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.16.0/sha256.sum | shasum --check --ignore-missing
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tar xvf zephyr-sdk-0.16.0_linux-x86_64.tar.xz
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cd zephyr-sdk-0.16.0
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./setup.sh
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```
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### LiteX
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1. Download `litex_setup.py` from the [LiteX repository][litex_repo], Upsilon
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@ -119,6 +93,21 @@ environment should be installed into the F4PGA conda environment,
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[litex_repo]: https://github.com/enjoy-digital/litex
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[sifive_gcc]: https://github.com/sifive/freedom-tools/releases
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### Buildroot
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Buildroot builds a Linux system for the FPGA. To build the Images, download a stable
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version of Buildroot that the config files support and run
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make BR2_EXTERNAL=/upsilon_directory/buildroot litex_vexriscv_defconfig
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### OpenSBI
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OpenSBI is a platform independent interface between the hardware and the kernel.
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Download the latest version of OpenSBI that the config files support. Copy
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the files in the `opensbi` directory to the `targets` directory and run
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make CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=litex/vexriscv
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## FPGA Build System
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Make sure F4PGA and a RISC-V GCC compiler are in your path. Then just go into
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@ -136,27 +125,9 @@ For the Arty A7, the bitstream is `firmware/build/digilent_arty/gateware/digilen
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## Software Build System
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The software build system uses files that are generated by the FPGA compile
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process. The number one reason why software won't work when loaded onto the
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FPGA is because it is compiled for a different FPGA bitstream. If you have
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an issue where software that you know should work does not, run `make clean`
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in the FPGA build system and rebuild it from scratch.
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It is recommended to use the [docker files][docker].
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This requires at least CMake 3.20.0 (you can install this using `conda`).
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Afterwards just run `make` and everything should work. Everything is
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managed by the `CMakeLists.txt` and the `prj.conf`, see the Zephyr OS
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documentation.
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The kernel is `/software/build/zephyr/zephyr.bin`
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If you make a change to `CMakeLists.txt` or to `prj.conf`, run `make clean`
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before `make`.
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Make can run in parallel using `-j${NUMBER_OF_PROCESSORS}`. Add this to the
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`buidl/zephyr/zephyr.bin` in `/software/Makefile` to makeyour builds faster.
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Remove this argument when you are attemping to fix compile errors and warnings
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(it will make the build output easier to read) but put it back when you fix
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them.
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[docker]: https://software.mcgoron.com/peter/upsilon-docker
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# Loading the Software and Firmware
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