From f0624bf664b6917c9ebf080d5eea72be2d1e017f Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Thu, 11 May 2023 11:43:30 -0400 Subject: [PATCH] adc debugging --- doc/programmers_manual.md | 38 ++++++++++++++++++++++++++++++++++++- firmware/rtl/base/base.v.m4 | 2 ++ firmware/soc.py | 2 ++ software/src/access.c | 10 ++++++++-- 4 files changed, 49 insertions(+), 3 deletions(-) diff --git a/doc/programmers_manual.md b/doc/programmers_manual.md index ccad906..5c8b440 100644 --- a/doc/programmers_manual.md +++ b/doc/programmers_manual.md @@ -418,8 +418,20 @@ interpreter. TODO +### Static IPs + +The client and controller IPs are baked into the software *and firmware* +at build time. The software configuration is in `software/prj.conf`. The +firmware configuration is in `firmware/soc.py` (see `local_ip` and `remote_ip` +settings in `SoCCore`). + +The controlling computer must have it's static IP on the interface connected +to the controller to be the same as `remote_ip`. By default this is `91.168.1.100`. + ## Logging +TODO: Do logging via UDP? + Logging is done via UART. Connect the micro-USB slot to the controlling computer to get debug output. @@ -500,6 +512,17 @@ write big Creole programs. The open source software stack that Upsilon uses is novel and unstable. +## LiteX + +Set `compile_software` to `False` in `soc.py` when checking for Verilog +compile errors. Set it back when you do an actual compile run, or your +program will not boot. + +If LiteX complains about not having a RiscV compiler, that is because +your system does not have compatible RISC-V compiler in your `$PATH`. +Refer to the LiteX install instructions above to see how to set up the +SiFive GCC, which will work. + ## F4PGA This is really a Yosys (and really, an abc bug). F4PGA defaults to using @@ -516,6 +539,18 @@ Yosys fails to calculate computed parameter values correctly. For instance, Yosys will *silently* fail to compile this, setting `VALUE` to be equal to 0. The solution is to use macros. +## Reset Pins + +On the Arty A7 there is a Reset button. This is connected to the CPU and only +resets the CPU. Possibly due to timing issues modules get screwed up if they +share a reset pin with the CPU. The code currently connects button 0 to reset +the modules seperately from the CPU. + +## Clock Speeds + +The output pins on the FPGA (except for the high speed PMOD outputs) cannot +switch fast enough to + ## Macros Verilog's preprocessor is awful. F4PGA (through yosys) barely supports it. @@ -559,7 +594,8 @@ static ip. each ip on the ethernet interface that is connected to the controller. 3. Run `ip addr add 192.168.1.100/24 dev eth-interface` (or whatever ip + subnet mask you need) -4. Run `ip route add 192.168.1.0/24 dev eth0 proto kernel scope link` (again, +4. If `ip route` does not give a routing entry for `192.168.1.0/24`, run + `ip route add 192.168.1.0/24 dev eth0 proto kernel scope link` (again, change depending on different situations) This will use the static ip `192.168.1.100`, which is the default TFTP boot diff --git a/firmware/rtl/base/base.v.m4 b/firmware/rtl/base/base.v.m4 index 041616f..4e86953 100644 --- a/firmware/rtl/base/base.v.m4 +++ b/firmware/rtl/base/base.v.m4 @@ -180,6 +180,8 @@ m4_define(m4_adc_switch, ⟨ /* 2nd option for each ADC is the non-converting option. * This is used to flush output from reset ADCs. + * TODO: Lower power consumption by having SCK low while converter is + * not running? May require change to spi code. */ assign adc_sdo_port[1] = adc_sdo_port[0]; assign adc_sck_port[1] = adc_sck_port[0]; diff --git a/firmware/soc.py b/firmware/soc.py index bf97b08..2ffa2c4 100644 --- a/firmware/soc.py +++ b/firmware/soc.py @@ -214,6 +214,8 @@ class CryoSNOM1SoC(SoCCore): csr_address_width=14, csr_paging=0x800, csr_ordering="big", + local_ip='192.168.1.50', + remote_ip='192.168.1.100', timer_uptime = True) # This initializes the connection to the physical DRAM interface. self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), diff --git a/software/src/access.c b/software/src/access.c index c2d1723..a6bf1f5 100644 --- a/software/src/access.c +++ b/software/src/access.c @@ -16,7 +16,7 @@ #include "access.h" #include "control_loop_cmds.h" -LOG_MODULE_REGISTER(access); +LOG_MODULE_REGISTER(access, 4); #include "pin_io.c" /* The values from converters are not aligned to 32 bits. @@ -126,10 +126,13 @@ adc_take(int adc, k_timeout_t timeout) if (adc < 0 || adc >= ADC_MAX) return -EFAULT; + LOG_DBG("%s: taking adc %d", get_thread_name(), adc); int e = k_mutex_lock(adc_mutex + adc, timeout); + LOG_DBG("%s: adc %d taken", get_thread_name(), adc); if (e == 0) { adc_locked[adc] += 1; } + LOG_DBG("%s: adc %d lockeg", get_thread_name(), adc); return e; } @@ -139,9 +142,10 @@ adc_release(int adc) if (adc < 0 || adc >= ADC_MAX) return -EFAULT; + LOG_DBG("%s: in adc_release", get_thread_name()); if (adc_locked[adc] == 1) { write_adc_arm(0, adc); - while (!read_adc_finished(adc)); + // while (!read_adc_finished(adc)); } int e = k_mutex_unlock(adc_mutex + adc); @@ -414,6 +418,7 @@ access_release_thread(void) void access_init(void) { + LOG_INF("access_init"); if (k_mutex_init(&cloop_mutex) != 0) { LOG_ERR("err: cloop mutex"); k_fatal_halt(K_ERR_KERNEL_PANIC); @@ -437,4 +442,5 @@ access_init(void) k_fatal_halt(K_ERR_KERNEL_PANIC); } } + LOG_INF("access_init done"); }