diff --git a/firmware/rtl/raster/ram_fifo.v b/firmware/rtl/raster/ram_fifo.v
index 40309d1..ac136c1 100644
--- a/firmware/rtl/raster/ram_fifo.v
+++ b/firmware/rtl/raster/ram_fifo.v
@@ -1,52 +1,30 @@
-/* YOSYS has a difficult time infering single port BRAM. It can infer
- * double-port block ram, however. This module is written as a double
- * port block ram, even though both clocks will end up being the same.
- * TODO:
- *   "empty" and "full" status indiciators for simulation
-
- * https://stackoverflow.com/questions/62703942/trouble-getting-yosys-to-infer-block-ram-array-rather-than-using-logic-cells-v
- * The answer by "TinLethax" infers a BRAM.
- */
 module ram_fifo #(
 	parameter DAT_WID = 24,
 	parameter FIFO_DEPTH = 1500,
 	parameter FIFO_DEPTH_WID = 11
 ) (
-	input RCLK,
-	input WCLK,
+	input clk,
 	input rst,
 
 	input read_enable,
 	input write_enable,
 
 	input signed [DAT_WID-1:0] write_dat,
-	output reg signed [DAT_WID-1:0] read_dat
+	output signed [DAT_WID-1:0] read_dat
 );
 
-reg [DAT_WID-1:0] memory [FIFO_DEPTH-1:0];
-initial memory[0] <= 24'b0;
-
-/* Read domain */
-
-reg [FIFO_DEPTH_WID-1:0] read_ptr = 0;
-always @ (posedge RCLK) begin
-	if (rst) begin
-		read_ptr <= 0;
-	end else if (read_enable) begin
-		read_dat <= memory[read_ptr];
-		read_ptr <= read_ptr + 1;
-	end
-end
-
-/* Write domain */
-reg [FIFO_DEPTH_WID-1:0] write_ptr = 0;
-always @ (posedge WCLK) begin
-	if (rst) begin
-		write_ptr <= 0;
-	end else if (write_enable) begin
-		memory[write_ptr] <= write_dat;
-		write_ptr <= write_ptr + 1;
-	end
-end
+ram_fifo_dual_port #(
+	.DAT_WID(DAT_WID),
+	.FIFO_DEPTH(FIFO_DEPTH),
+	.FIFO_DEPTH_WID(FIFO_DEPTH_WID)
+) m (
+	.WCLK(clk),
+	.RCLK(clk),
+	.rst(rst),
+	.read_enable(read_enable),
+	.write_enable(write_enable),
+	.write_dat(write_dat),
+	.read_dat(read_dat)
+);
 
 endmodule
diff --git a/firmware/rtl/raster/ram_fifo_dual_port.v b/firmware/rtl/raster/ram_fifo_dual_port.v
new file mode 100644
index 0000000..75ac144
--- /dev/null
+++ b/firmware/rtl/raster/ram_fifo_dual_port.v
@@ -0,0 +1,52 @@
+/* YOSYS has a difficult time infering single port BRAM. It can infer
+ * double-port block ram, however. This module is written as a double
+ * port block ram, even though both clocks will end up being the same.
+ * TODO:
+ *   "empty" and "full" status indiciators for simulation
+
+ * https://stackoverflow.com/questions/62703942/trouble-getting-yosys-to-infer-block-ram-array-rather-than-using-logic-cells-v
+ * The answer by "TinLethax" infers a BRAM.
+ */
+module ram_fifo_dual_port #(
+	parameter DAT_WID = 24,
+	parameter FIFO_DEPTH = 1500,
+	parameter FIFO_DEPTH_WID = 11
+) (
+	input RCLK,
+	input WCLK,
+	input rst,
+
+	input read_enable,
+	input write_enable,
+
+	input signed [DAT_WID-1:0] write_dat,
+	output reg signed [DAT_WID-1:0] read_dat
+);
+
+reg [DAT_WID-1:0] memory [FIFO_DEPTH-1:0];
+initial memory[0] <= 24'b0;
+
+/* Read domain */
+
+reg [FIFO_DEPTH_WID-1:0] read_ptr = 0;
+always @ (posedge RCLK) begin
+	if (rst) begin
+		read_ptr <= 0;
+	end else if (read_enable) begin
+		read_dat <= memory[read_ptr];
+		read_ptr <= read_ptr + 1;
+	end
+end
+
+/* Write domain */
+reg [FIFO_DEPTH_WID-1:0] write_ptr = 0;
+always @ (posedge WCLK) begin
+	if (rst) begin
+		write_ptr <= 0;
+	end else if (write_enable) begin
+		memory[write_ptr] <= write_dat;
+		write_ptr <= write_ptr + 1;
+	end
+end
+
+endmodule