buildroot

This commit is contained in:
Peter McGoron 2023-05-26 17:17:59 -04:00
parent 5178594215
commit f46cd98483
7 changed files with 137 additions and 0 deletions

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The files "board/litex_vexriscv/linux.config" and
"configs/litex_vexriscv_defconfig" incorporate code from
https://github.com/litex-hub/linux-on-litex-vexriscv
________________________________________________________________________
BSD 2-Clause License
Copyright (c) 2019-2021, Linux-on-LiteX-VexRiscv Developers
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# Architecture
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
CONFIG_NONPORTABLE=y
CONFIG_ARCH_RV32I=y
CONFIG_RISCV_ISA_M=y
CONFIG_RISCV_ISA_A=y
CONFIG_RISCV_ISA_C=n
CONFIG_SIFIVE_PLIC=y
CONFIG_FPU=n
CONFIG_SMP=n
CONFIG_STRICT_KERNEL_RWX=n
CONFIG_EFI=n
CONFIG_HVC_RISCV_SBI=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# FPGA / SoC
CONFIG_FPGA=y
CONFIG_FPGA_MGR_LITEX=y
CONFIG_LITEX_SOC_CONTROLLER=y
CONFIG_LITEX_SUBREG_SIZE=4
# Time
CONFIG_PRINTK_TIME=y
# Clocking
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_LITEX=y
# Interrupts
CONFIG_IRQCHIP=y
CONFIG_OF_IRQ=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_LITEX_VEXRISCV_INTC=y
# Ethernet
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_INET=y
CONFIG_NETDEVICES=y
CONFIG_NET_VENDOR_LITEX=y
CONFIG_LITEX_LITEETH=y
# Serial
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_SERIAL_LITEUART=y
CONFIG_SERIAL_LITEUART_CONSOLE=y
# Hardware monitoring
CONFIG_HWMON=y
CONFIG_SENSORS_LITEX_HWMON=y
# Framebuffer
CONFIG_FB=y
CONFIG_FB_SIMPLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# .config in kernel
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# Filesystem
CONFIG_TMPFS=y

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Upsilon on Linux, LiteX VexRiscV

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#Target options
BR2_riscv=y
BR2_RISCV_32=y
# Instruction Set Extensions
BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y
BR2_RISCV_ISA_CUSTOM_RVC=n
BR2_RISCV_ABI_ILP32=y
# GCC
BR2_GCC_VERSION_10_X=y
BR2_BINUTILS_VERSION_2_37_X=y
# System
BR2_TARGET_GENERIC_GETTY=y
BR2_TARGET_GENERIC_GETTY_PORT="console"
# Filesystem
BR2_TARGET_ROOTFS_CPIO=y
# Kernel (litex-rebase branch)
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_UPSILON_PATH)/board/litex_vexriscv/linux.config"
BR2_LINUX_KERNEL_IMAGE=y
# Rootfs customisation
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_UPSILON_PATH)/board/litex_vexriscv/rootfs_overlay"
# Extra packages
BR2_PACKAGE_MICROPYTHON=y
BR2_PACKAGE_MICROPYTHON_LIB=y

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name: UPSILON

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buildroot/external.mk Normal file
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