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control_loop: remove reg keyword, yosys doesnt like it

This commit is contained in:
Peter McGoron 2022-12-17 09:56:26 -05:00
parent 644f4142a2
commit f536a41784
1 changed files with 3 additions and 3 deletions
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6
firmware/rtl/control_loop/control_loop.v
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@ -49,8 +49,8 @@ module control_loop
output adc_sck,
/* Hacky ad-hoc read-write interface. */
input reg [`CONTROL_LOOP_CMD_WIDTH-1:0] cmd,
input reg [`DATA_WID-1:0] word_in,
input [`CONTROL_LOOP_CMD_WIDTH-1:0] cmd,
input [`DATA_WID-1:0] word_in,
output reg [`DATA_WID-1:0] word_out,
input start_cmd,
output reg finish_cmd
@ -150,7 +150,7 @@ wire signed [`CONSTS_WID-1:0] adj_val;
wire signed [DAC_DATA_WID-1:0] new_dac_val;
reg arm_math = 0;
reg math_finished = 0;
wire math_finished;
control_loop_math #(
.CONSTS_WHOLE(CONSTS_WHOLE),
.CONSTS_FRAC(CONSTS_FRAC),