remove explicit finalize, is not needed and probably out of order

2024-02-04 14:50:19 +00:00 · 2024-02-04 14:50:19 +00:00 · f7d6fbee2f
parent c3980f64da
commit f7d6fbee2f
1 changed files with 0 additions and 1 deletions
--- a/gateware/soc.py
+++ b/gateware/soc.py
@ -424,7 +424,6 @@ class UpsilonSoC(SoCCore):
        self.submodules.picorv32 = pr = PicoRV32()
        self.bus.add_slave("picorv32_master_bram", pr.bram_iface.buses[0],
                SoCRegion(size=pr.bram.region.size, cached=True))
-        pr.finalize()

    def __init__(self,
                 variant="a7-100",