From fbbd41c95ef5a22692c09553768174c07cdf7c8e Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Wed, 15 Mar 2023 14:57:08 -0400 Subject: [PATCH] codegen --- firmware/Makefile | 8 ++++---- firmware/rtl/Makefile | 10 ++++++++++ firmware/rtl/base/Makefile | 2 ++ firmware/rtl/spi/Makefile | 2 +- firmware/soc.py | 2 +- 5 files changed, 18 insertions(+), 6 deletions(-) create mode 100644 firmware/rtl/Makefile diff --git a/firmware/Makefile b/firmware/Makefile index 98386b0..895a3f9 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -2,11 +2,11 @@ DEVICETREE_GEN_DIR=. -all: rtl/base/base.v build/digilent_arty/digilent_arty.bit overlay.dts overlay.config pin_io.h +all: rtl_codegen build/digilent_arty/digilent_arty.bit overlay.dts overlay.config pin_io.h -rtl/base/base.v: - cd rtl/base && make -build/digilent_arty/digilent_arty.bit: rtl/base/base.v soc.py +rtl_codegen: + cd rtl && make +build/digilent_arty/digilent_arty.bit: rtl_codegen soc.py python3 soc.py clean: rm -rf build csr.json overlay.config overlay.dts pin_io.h diff --git a/firmware/rtl/Makefile b/firmware/rtl/Makefile new file mode 100644 index 0000000..c4e3589 --- /dev/null +++ b/firmware/rtl/Makefile @@ -0,0 +1,10 @@ +all: make_base make_control_loop make_waveform + +make_base: + cd base && make codegen +make_spi: + cd spi && make codegen +make_control_loop: + cd control_loop && make codegen +make_waveform: + cd waveform && make codegen diff --git a/firmware/rtl/base/Makefile b/firmware/rtl/base/Makefile index 359758f..658ace2 100644 --- a/firmware/rtl/base/Makefile +++ b/firmware/rtl/base/Makefile @@ -1,5 +1,7 @@ .PHONY: lint include ../common.makefile + +codegen: base.v base.v: base.v.m4 lint: base.v verilator --lint-only base.v -I../spi -I../control_loop -I../waveform diff --git a/firmware/rtl/spi/Makefile b/firmware/rtl/spi/Makefile index 8be90d2..587a054 100644 --- a/firmware/rtl/spi/Makefile +++ b/firmware/rtl/spi/Makefile @@ -6,7 +6,7 @@ all: test codegen test: obj_dir/Vspi_switch codegen: spi_master_ss_preprocessed.v spi_master_preprocessed.v \ - spi_master_ss_no_write_preprocessed.v + spi_master_ss_no_write_preprocessed.v spi_switch_preprocessed.v %_preprocessed.v: %.v verilator -E $< > $@ diff --git a/firmware/soc.py b/firmware/soc.py index f23e804..c527751 100644 --- a/firmware/soc.py +++ b/firmware/soc.py @@ -332,7 +332,7 @@ class CryoSNOM1SoC(SoCCore): csr_address_width=14, csr_paging=0x800, csr_ordering="big", - timer_uptime = True)e + timer_uptime = True) # This initializes the connection to the physical DRAM interface. self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3",