diff --git a/firmware/generate_csr_locations.py b/firmware/generate_csr_locations.py
index 710f6ec..e740d34 100644
--- a/firmware/generate_csr_locations.py
+++ b/firmware/generate_csr_locations.py
@@ -118,14 +118,14 @@ if __name__ == "__main__":
 		(False, "dac_arm", dac_num),
 		(True, "from_dac", dac_num),
 		(False, "to_dac", dac_num),
-		(False, "wf_arm", dac_num),
-		(False, "wf_halt_on_finish", dac_num),
-		(True, "wf_finished", dac_num),
-		(True, "wf_running", dac_num),
-		(False, "wf_time_to_wait", dac_num),
-		(False, "wf_refresh_start", dac_num),
-		(True, "wf_refresh_finished", dac_num),
-		(False, "wf_start_addr", dac_num),
+#		(False, "wf_arm", dac_num),
+#		(False, "wf_halt_on_finish", dac_num),
+#		(True, "wf_finished", dac_num),
+#		(True, "wf_running", dac_num),
+#		(False, "wf_time_to_wait", dac_num),
+#		(False, "wf_refresh_start", dac_num),
+#		(True, "wf_refresh_finished", dac_num),
+#		(False, "wf_start_addr", dac_num),
 
 		(True, "adc_finished", adc_num),
 		(False, "adc_arm", adc_num),
diff --git a/firmware/rtl/base/base.v.m4 b/firmware/rtl/base/base.v.m4
index e0c9764..0e49f21 100644
--- a/firmware/rtl/base/base.v.m4
+++ b/firmware/rtl/base/base.v.m4
@@ -24,8 +24,9 @@ m4_define(m4_dac_wires, ⟨
 	output dac_finished_$2,
 	input dac_arm_$2,
 	output [DAC_WID-1:0] from_dac_$2,
-	input [DAC_WID-1:0] to_dac_$2,
+	input [DAC_WID-1:0] to_dac_$2
 
+/*
 	input wf_arm_$2,
 	input wf_halt_on_finish_$2,
 	output wf_finished_$2,
@@ -39,6 +40,7 @@ m4_define(m4_dac_wires, ⟨
 	input [WF_RAM_WORD_WID-1:0] wf_ram_word_$2,
 	output wf_ram_read_$2,
 	input wf_ram_valid_$2
+*/
 ⟩)
 
 /* Same thing but for ADCs */
@@ -97,8 +99,9 @@ m4_define(m4_dac_switch, ⟨
 		.arm(dac_arm_$2),
 		.from_slave(from_dac_$2),
 		.to_slave(to_dac_$2)
-	);
+	)
 
+/*
 	waveform #(
 		.DAC_WID(DAC_WID),
 		.DAC_WID_SIZ(DAC_WID_SIZ),
@@ -133,6 +136,7 @@ m4_define(m4_dac_switch, ⟨
 		.sck(sck_port_$2[1]),
 		.ss_L(ss_L_port_$2[1])
 	)
+*/
 ⟩)
 
 /* Same thing but for ADCs */
@@ -194,7 +198,7 @@ m4_define(m4_adc_switch, ⟨
 /*********************************************************/
 
 module base #(
-	parameter DAC_PORTS = 2,
+	parameter DAC_PORTS = 1,
 m4_define(DAC_PORTS_CONTROL_LOOP, (DAC_PORTS + 1))
 
 	parameter DAC_NUM = 8,
@@ -357,10 +361,10 @@ control_loop #(
 	.clk(clk),
 	.rst_L(rst_L),
 	.in_loop(cl_in_loop),
-	.dac_mosi(mosi_port_0[2]),
-	.dac_miso(miso_port_0[2]),
-	.dac_ss_L(ss_L_port_0[2]),
-	.dac_sck(sck_port_0[2]),
+	.dac_mosi(mosi_port_0[1]),
+	.dac_miso(miso_port_0[1]),
+	.dac_ss_L(ss_L_port_0[1]),
+	.dac_sck(sck_port_0[1]),
 	.adc_miso(adc_sdo_port_0[2]),
 	.adc_conv_L(adc_conv_L_port_0[2]),
 	.adc_sck(adc_sck_port_0[2]),
diff --git a/firmware/soc.py b/firmware/soc.py
index d4b2a5b..3dd9302 100644
--- a/firmware/soc.py
+++ b/firmware/soc.py
@@ -143,23 +143,23 @@ class Base(Module, AutoCSR):
 			self._make_csr("dac_arm", CSRStorage, 1, f"DAC {i} Arm Flag", num=i)
 			self._make_csr("from_dac", CSRStatus, 24, f"DAC {i} Received Data", num=i)
 			self._make_csr("to_dac", CSRStorage, 24, f"DAC {i} Data to Send", num=i)
-			self._make_csr("wf_arm", CSRStorage, 1, f"Waveform {i} Arm Flag", num=i)
-			self._make_csr("wf_halt_on_finish", CSRStorage, 1, f"Waveform {i} Halt on Finish Flag", num=i)
-			self._make_csr("wf_finished", CSRStatus, 1, f"Waveform {i} Finished Flag", num=i)
-			self._make_csr("wf_running", CSRStatus, 1, f"Waveform {i} Running Flag", num=i)
-			self._make_csr("wf_time_to_wait", CSRStorage, 16, f"Waveform {i} Wait Time", num=i)
-			self._make_csr("wf_refresh_start", CSRStorage, 1, f"Waveform {i} Data Refresh Start Flag", num=i)
-			self._make_csr("wf_refresh_finished", CSRStatus, 1, f"Waveform {i} Data Refresh Finished Flag", num=i)
-			self._make_csr("wf_start_addr", CSRStorage, 32, f"Waveform {i} Data Addr", num=i)
-
-			port = sdram.crossbar.get_port()
-			setattr(self, f"wf_sdram_{i}", LiteDRAMDMAReader(port))
-			cur_sdram = getattr(self, f"wf_sdram_{i}")
-
-			self.kwargs[f"o_wf_ram_dma_addr_{i}"] = cur_sdram.sink.address
-			self.kwargs[f"i_wf_ram_word_{i}"] = cur_sdram.source.data
-			self.kwargs[f"o_wf_ram_read_{i}"] = cur_sdram.sink.valid
-			self.kwargs[f"i_wf_ram_valid_{i}"] = cur_sdram.source.valid
+#			self._make_csr("wf_arm", CSRStorage, 1, f"Waveform {i} Arm Flag", num=i)
+#			self._make_csr("wf_halt_on_finish", CSRStorage, 1, f"Waveform {i} Halt on Finish Flag", num=i)
+#			self._make_csr("wf_finished", CSRStatus, 1, f"Waveform {i} Finished Flag", num=i)
+#			self._make_csr("wf_running", CSRStatus, 1, f"Waveform {i} Running Flag", num=i)
+#			self._make_csr("wf_time_to_wait", CSRStorage, 16, f"Waveform {i} Wait Time", num=i)
+#			self._make_csr("wf_refresh_start", CSRStorage, 1, f"Waveform {i} Data Refresh Start Flag", num=i)
+#			self._make_csr("wf_refresh_finished", CSRStatus, 1, f"Waveform {i} Data Refresh Finished Flag", num=i)
+#			self._make_csr("wf_start_addr", CSRStorage, 32, f"Waveform {i} Data Addr", num=i)
+#
+#			port = sdram.crossbar.get_port()
+#			setattr(self, f"wf_sdram_{i}", LiteDRAMDMAReader(port))
+#			cur_sdram = getattr(self, f"wf_sdram_{i}")
+#
+#			self.kwargs[f"o_wf_ram_dma_addr_{i}"] = cur_sdram.sink.address
+#			self.kwargs[f"i_wf_ram_word_{i}"] = cur_sdram.source.data
+#			self.kwargs[f"o_wf_ram_read_{i}"] = cur_sdram.sink.valid
+#			self.kwargs[f"i_wf_ram_valid_{i}"] = cur_sdram.source.valid
 
 			self._make_csr("adc_finished", CSRStatus, 1, f"ADC {i} Finished Flag", num=i)
 			self._make_csr("adc_arm", CSRStorage, 1, f"ADC {i} Arm Flag", num=i)
@@ -245,8 +245,8 @@ class UpsilonSoC(SoCCore):
 		platform.add_source("rtl/control_loop/boothmul_preprocessed.v")
 		platform.add_source("rtl/control_loop/control_loop_math.v")
 		platform.add_source("rtl/control_loop/control_loop.v")
-		platform.add_source("rtl/waveform/bram_interface_preprocessed.v")
-		platform.add_source("rtl/waveform/waveform_preprocessed.v")
+#		platform.add_source("rtl/waveform/bram_interface_preprocessed.v")
+#		platform.add_source("rtl/waveform/waveform_preprocessed.v")
 		platform.add_source("rtl/base/base.v")
 
 		# SoCCore does not have sane defaults (no integrated rom)