Peter McGoron
|
fd1df03506
|
comment out waveform modules
|
2023-06-02 18:30:15 -04:00 |
Peter McGoron
|
5178594215
|
proper CSR location generation
|
2023-05-16 15:02:05 -04:00 |
Peter McGoron
|
d0ec4cca9e
|
convert differential outputs to single ended outputs
|
2023-05-11 16:47:24 -04:00 |
Peter McGoron
|
0a9125355f
|
disable test clock by default
|
2023-05-11 15:31:52 -04:00 |
Peter McGoron
|
f0624bf664
|
adc debugging
|
2023-05-11 11:43:30 -04:00 |
Peter McGoron
|
15b8fcbe7e
|
reset pins and test clock
|
2023-05-10 14:35:57 -04:00 |
Peter McGoron
|
40fd1ab6fe
|
add debug clock
|
2023-04-20 15:20:42 -04:00 |
Peter McGoron
|
e19a626945
|
dac, adc switch and documentation
|
2023-04-04 15:10:32 -04:00 |
Peter McGoron
|
11f7cfd388
|
refactor soc.py base.v interface
|
2023-04-02 21:35:51 +00:00 |
Peter McGoron
|
55fc252382
|
pass yosys
|
2023-03-15 17:08:55 -04:00 |
Peter McGoron
|
953e42b80c
|
change control_loop to m4 scripts, add common makefile
|
2023-03-15 18:30:08 +00:00 |