Commit Graph

3 Commits

Author SHA1 Message Date
Peter McGoron 88e3d15dd8 Get PicoRV32 to execute code
1. Update LiteX to 2023.12. This update adds wishbone bus addressing
   modes. Before this update, all wishbone buses used word addressing.
   For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This
   caused problems with the PicoRV32 and other modules, which are byte
   addressed.
2. Use adapter to convert between byte and word addressing. The SRAM is
   word addressed. The PicoRV32 shifts the address down by two bits to
   address the correct word. The PicoRV32 core seems to expect this.
3. Add debug register output. This is not working yet.
4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This
   seems to be simpler (combinatorial not synchronous).
5. Add some documentation.
6. Seperate config to new config file.
2024-02-25 18:58:34 +00:00
Peter McGoron 4e3df09bb8 more cleanup and bug finding 2024-02-08 12:57:22 +00:00
Peter McGoron beeb9a5b91 rename hardware docker file 2023-06-20 13:09:27 -04:00