1. Started writing a lot of documentation on how Upsilon is
structured. This will replace the very outdated documentation.
2. Fixed parameter access and writing. This is also a more generic
interface that can be used for Pico CPUs that implement different
routines.
1. Update LiteX to 2023.12. This update adds wishbone bus addressing
modes. Before this update, all wishbone buses used word addressing.
For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This
caused problems with the PicoRV32 and other modules, which are byte
addressed.
2. Use adapter to convert between byte and word addressing. The SRAM is
word addressed. The PicoRV32 shifts the address down by two bits to
address the correct word. The PicoRV32 core seems to expect this.
3. Add debug register output. This is not working yet.
4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This
seems to be simpler (combinatorial not synchronous).
5. Add some documentation.
6. Seperate config to new config file.
Peter McGoron