 Peter McGoron
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0f86a60510
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compile verilog
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2023-04-03 15:29:20 -04:00 |
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Peter McGoron
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11f7cfd388
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refactor soc.py base.v interface
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2023-04-02 21:35:51 +00:00 |
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Peter McGoron
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55fc252382
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pass yosys
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2023-03-15 17:08:55 -04:00 |
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Peter McGoron
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fbbd41c95e
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codegen
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2023-03-15 14:57:22 -04:00 |
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Peter McGoron
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ca8078f9d6
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quick hack: pre-prepreprocess verilog files
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2023-03-15 18:47:20 +00:00 |
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Peter McGoron
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7af907ffb4
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soc.py: fix syntax errors
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2023-03-15 03:04:27 -04:00 |
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Peter McGoron
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fefa6409cf
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soc.py: add missing waveform pins
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2023-03-15 06:30:59 +00:00 |
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Peter McGoron
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90a49b6091
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test and simulate spi_switch
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2023-03-14 15:42:41 +00:00 |
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Peter McGoron
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295eb8fad8
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add base.v
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2023-03-09 04:17:41 +00:00 |
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Peter McGoron
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7ca119d45f
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soc.py legal
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2022-09-17 00:58:15 -04:00 |
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Peter McGoron
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01cbcb5fae
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add verilog SPI
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2022-07-21 17:07:52 -04:00 |
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Peter McGoron
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592939f5bd
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change pinout
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2022-07-14 15:10:58 -04:00 |
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Peter McGoron
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930b5ec8af
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cleanup
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2022-07-12 13:30:28 -04:00 |