Commit Graph

6 Commits

Author SHA1 Message Date
Peter McGoron 6b9e594b50 Successfully read PicoRV32 registers 2024-02-26 00:47:43 +00:00
Peter McGoron 88e3d15dd8 Get PicoRV32 to execute code
1. Update LiteX to 2023.12. This update adds wishbone bus addressing
   modes. Before this update, all wishbone buses used word addressing.
   For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This
   caused problems with the PicoRV32 and other modules, which are byte
   addressed.
2. Use adapter to convert between byte and word addressing. The SRAM is
   word addressed. The PicoRV32 shifts the address down by two bits to
   address the correct word. The PicoRV32 core seems to expect this.
3. Add debug register output. This is not working yet.
4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This
   seems to be simpler (combinatorial not synchronous).
5. Add some documentation.
6. Seperate config to new config file.
2024-02-25 18:58:34 +00:00
Peter McGoron d76c1f8ad1 documentation 2023-06-21 17:04:54 -04:00
Peter McGoron dc1e8bae8c docker documentation 2023-06-20 13:23:43 -04:00
Peter McGoron 9c9b28116e documentation 2023-06-15 13:08:01 -04:00
Peter McGoron cd3f6d8cf9 move GUIDELINES.md to doc/verilog_manual.md 2023-06-15 11:46:48 -04:00