 Peter McGoron
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7a341a9632
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yosys does not like calculated parameters
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2022-10-30 15:37:45 -04:00 |
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Peter McGoron
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ba901a80d7
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separate math into other file
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2022-10-28 17:31:23 -04:00 |
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Peter McGoron
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4f85146d61
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add cycle count for each iteration
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2022-10-23 14:21:31 -04:00 |
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Peter McGoron
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0a435f6dc8
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rename control loop verilog simulation top level module to more descriptive name
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2022-10-22 01:58:37 -04:00 |
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Peter McGoron
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7971f8ea98
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change heading
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2022-10-22 01:55:56 -04:00 |
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Peter McGoron
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644929ef8a
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move documentation to other file
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2022-10-22 01:55:15 -04:00 |
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Peter McGoron
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91cbf56b02
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integrate adding stored dac value into rtrunc
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2022-10-22 01:52:58 -04:00 |
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Peter McGoron
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f361cac01b
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make values update on the start of the control loop, and make resets only take effect after the control loop has completed an iteration
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2022-10-21 17:38:07 -04:00 |
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Peter McGoron
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12686391ee
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use integer saturation for dac value adjustment
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2022-10-20 19:43:13 -04:00 |
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Peter McGoron
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2a300b9438
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write total value to dac, not adjustment vlaue
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2022-10-20 15:42:24 -04:00 |
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Peter McGoron
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c42e2fe419
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add write-read interface to control loop
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2022-10-18 07:10:06 -04:00 |
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Peter McGoron
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dc2b1fe339
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move SPI master out of control loop design
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2022-10-17 14:37:37 -04:00 |
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Peter McGoron
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0ef00c15d7
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move simulators to the same directory of the simulated core
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2022-10-17 00:45:19 -04:00 |
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Peter McGoron
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029cc53c5f
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some more changes
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2022-10-17 00:44:30 -04:00 |
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Peter McGoron
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5125719a1f
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move control loop stub code to control loop rtl
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2022-10-12 08:48:34 -04:00 |
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Peter McGoron
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0298299402
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add everything im working on
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2022-09-16 18:01:34 -04:00 |