 Peter McGoron
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55fc252382
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pass yosys
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2023-03-15 17:08:55 -04:00 |
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Peter McGoron
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fbbd41c95e
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codegen
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2023-03-15 14:57:22 -04:00 |
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Peter McGoron
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ca8078f9d6
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quick hack: pre-prepreprocess verilog files
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2023-03-15 18:47:20 +00:00 |
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Peter McGoron
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c8f2cf1f7a
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spi_switch: fix dangling else
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2023-03-14 15:43:34 +00:00 |
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Peter McGoron
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90a49b6091
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test and simulate spi_switch
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2023-03-14 15:42:41 +00:00 |
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Peter McGoron
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36e5b964d5
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lint base.v
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2023-03-14 04:06:42 +00:00 |
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Peter McGoron
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295eb8fad8
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add base.v
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2023-03-09 04:17:41 +00:00 |
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Peter McGoron
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89938a2ff6
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move autoapproach to possibly useful waveform module: not yet tested
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2023-03-03 18:30:00 +00:00 |
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Peter McGoron
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05f8878751
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add submodules and switch
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2023-03-03 08:06:50 +00:00 |
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Peter McGoron
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33ec8351d8
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correctly (and crudely) simulate control loop
Issue was that the ADC cycle half wait (SCK delay) was too fast
for the input buffering (since MISO and MOSI are physical inputs
and not FPGA wires).
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2022-11-24 09:48:19 -05:00 |
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Peter McGoron
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5909f548d5
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control loop simulator passes lint
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2022-11-21 21:41:50 -05:00 |
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Peter McGoron
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82ff659a44
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add DAC ramp
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2022-11-17 17:32:32 -05:00 |
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Peter McGoron
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0907a76c22
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import spi v0.2
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2022-11-14 08:43:16 -05:00 |
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Peter McGoron
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029cc53c5f
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some more changes
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2022-10-17 00:44:30 -04:00 |
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Peter McGoron
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0298299402
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add everything im working on
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2022-09-16 18:01:34 -04:00 |
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Peter McGoron
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01cbcb5fae
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add verilog SPI
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2022-07-21 17:07:52 -04:00 |