 Peter McGoron
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1ed48fbc90
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control_loop_sim: add comments
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2022-11-24 10:08:00 -05:00 |
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Peter McGoron
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cef639784b
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control_loop_sim: modify second P value
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2022-11-24 10:00:05 -05:00 |
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Peter McGoron
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1d54b41735
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fix bit width bug
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2022-11-24 09:55:15 -05:00 |
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Peter McGoron
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33ec8351d8
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correctly (and crudely) simulate control loop
Issue was that the ADC cycle half wait (SCK delay) was too fast
for the input buffering (since MISO and MOSI are physical inputs
and not FPGA wires).
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2022-11-24 09:48:19 -05:00 |
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Peter McGoron
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5ff6b279b0
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reverify math
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2022-11-21 22:24:37 -05:00 |
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Peter McGoron
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cfb0f92528
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fix adc_sim
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2022-11-21 22:04:46 -05:00 |
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Peter McGoron
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5909f548d5
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control loop simulator passes lint
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2022-11-21 21:41:50 -05:00 |
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Peter McGoron
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45f815c5d3
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changes
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2022-11-11 21:57:58 -05:00 |
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Peter McGoron
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029cc53c5f
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some more changes
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2022-10-17 00:44:30 -04:00 |
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Peter McGoron
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5125719a1f
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move control loop stub code to control loop rtl
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2022-10-12 08:48:34 -04:00 |