102 lines
2.7 KiB
Verilog
102 lines
2.7 KiB
Verilog
module raster #(
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parameter SAMPLEWID = 9,
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parameter DAC_DATA_WID = 20,
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parameter DAC_WID = 24,
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parameter STEPWID = 16,
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parameter MAX_ADC_DATA_WID = 24
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) (
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input clk,
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input arm,
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/* Amount of steps per sample. */
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input [STEPWID-1:0] steps,
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/* Amount of samples in one line (forward) */
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input [SAMPLEWID-1:0] samples,
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/* Amount of lines in the output. */
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input [SAMPLEWID-1:0] lines,
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/* Each step goes (x,y) -> (dx,dy) forward for each line of
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* the output. */
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input signed [DAC_DATA_WID-1:0] dx,
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input signed [DAC_DATA_WID-1:0] dy,
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/* Vertical steps to go to the next line. */
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input signed [DAC_DATA_WID-1:0] dx_vert,
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input signed [DAC_DATA_WID-1:0] dy_vert,
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/* X and Y DAC piezos */
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input x_ready,
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output [DACWID-1:0] x_to_dac,
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input [DACWID-1:0] x_from_dac,
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output x_finished,
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input y_ready,
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output [DACWID-1:0] y_to_dac,
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input [DACWID-1:0] y_from_dac,
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output y_finished,
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/* Connections to all possible ADCs. These are connected to SPI masters
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* and they will automatically extend ADC value lengths to their highest
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* values. */
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input adc_in [0:ADCNUM-1],
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output [MAX_ADC_DATA_WID-1:0] adc_conv [0:ADCNUM-1],
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output adc_finished [0:ADCNUM-1],
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/* Bitmap for which ADCs are used. */
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input [ADCNUM-1:0] adc_used,
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output signed [MAX_ADC_DATA_WID-1:0] fifo_data,
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output fifo_ready,
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input fifo_valid
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);
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/* State machine:
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┏━━━━ WAIT ON ARM
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↑ ↓ (arm -> 1)
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┃ GET DAC VALUES
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┃ ↓ (when x and y values are obtained)
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┃ ┏━LOOP FORWARD WITHOUT MEASUREMENT
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┃ ↑ ↓ (when enough steps are taken)
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┃ ┃ GET ADC VALUES
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┃ ┃ ↓ (when all ADC values are obtained)
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┃ ┃ SEND THROUGH FIFO
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┃ ┃ ↓ (when finished)
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┃ ┏━┫ ┃
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┃ ↑ ┗━━━←━┫
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┃ ┃ ┃ (when at the end of a line)
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┃ ┃ ┃
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┃ ┃ ┏━LOOP BACKWARD WITHOUT MEASUREMENT
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┃ ┃ ↑ ↓ (when enough steps are taken)
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┃ ┃ ┃ GET ADC VALUES, BACKWARDS MEASUREMENT
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┃ ┃ ┃ ↓ (when all ADC values are obtained)
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┃ ┃ ┃ SEND THROUGH FIFO, BACKWARDS MEASUREMENT
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┃ ┃ ┃ ↓ (when finished)
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┃ ┃ ┃ ┃
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┃ ┃ ┗━━━←━┫
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┃ ┃ ↓
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┃ ┗━━━━━━━┫
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┃ ↓ (when the image is finished)
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┃ ┃
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┃ WAIT FOR ARM DEASSERT
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┃ ↓ (when arm = 0)
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┗━━━━━━━━━┛
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*/
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localparam WAIT_ON_ARM = 0;
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localparam GET_DAC_VALUES = 1;
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localparam INCREMENT_XVAL = 2;
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localparam GET_ADC_VAL = 3;
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localparam SEND_FIFO = 4;
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localparam WAIT_FOR_REARM = 5;
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reg [2:0] stepstate = WAIT_ON_ARM;
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reg is_forward = 1;
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reg [SAMPLEWID-1:0] samplenum;
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reg [STEPWID-1:0] stepnum;
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always @ (posedge clk) begin
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end
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endmodule
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