97 lines
2.1 KiB
Verilog
97 lines
2.1 KiB
Verilog
module autoapproach_sim #(
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parameter DAC_WID = 24,
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parameter DAC_DATA_WID = 20,
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parameter ADC_WID = 24,
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parameter TIMER_WID = 32,
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parameter WORD_WID = 24,
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parameter WORD_AMNT_WID = 11,
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parameter [WORD_AMNT_WID-1:0] WORD_AMNT = 2047,
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parameter RAM_WID = 32,
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parameter RAM_WORD_WID = 16,
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parameter RAM_WORD_INCR = 2,
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parameter TOTAL_RAM_WORD_MINUS_ONE = 4095
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) (
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input clk,
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input arm,
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output stopped,
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output detected,
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input polarity,
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input [ADC_WID-1:0] setpoint,
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input [TIMER_WID-1:0] time_to_wait,
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/* User interface */
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input refresh_start,
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input [RAM_WID-1:0] start_addr,
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output refresh_finished,
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/* DAC wires. */
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input dac_finished,
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output dac_arm,
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output [DAC_WID-1:0] dac_out,
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input adc_finished,
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output adc_arm,
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input [ADC_WID-1:0] measurement
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input[RAM_WORD_WID-1:0] backing_store [TOTAL_RAM_WORD_MINUS_ONE:0]
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);
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wire [RAM_WID-1:0] ram_dma_addr;
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wire [RAM_WORD_WID-1:0] ram_word;
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wire ram_read;
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wire ram_valid;
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dma_sim #(
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.RAM_WID(RAM_WID),
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.RAM_WORD_WID(RAM_WORD_WID),
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.RAM_REAL_START(RAM_REAL_START),
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.RAM_CNTR_LEN(RAM_CNTR_LEN),
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.TOTAL_RAM_WORD_MINUS_ONE(TOTAL_RAM_WORD_MINUS_ONE),
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.DELAY_CNTR_LEN(DELAY_CNTR_LEN),
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.DELAY_TOTAL(DELAY_TOTAL)
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) dma_sim (
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.clk(clk),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid),
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.backing_store(backing_store)
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);
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autoapproach #(
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.DAC_WID(DAC_WID),
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.DAC_DATA_WID(DAC_DATA_WID),
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.ADC_WID(ADC_WID),
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.TIMER_WID(TIMER_WID),
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.WORD_WID(WORD_WID),
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.WORD_AMNT_WID(WORD_AMNT_WID),
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.WORD_AMNT(WORD_AMNT),
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.RAM_WID(RAM_WID),
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.RAM_WORD_WID(RAM_WORD_WID),
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.RAM_WORD_INCR(RAM_WORD_INCR)
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) aa (
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.clk(clk),
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.arm(arm),
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.stopped(stopped),
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.detected(detected),
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.polarity(polarity),
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.setpoint(setpoint),
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.time_to_wait(time_to_wait),
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.refresh_start(refresh_start),
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.start_addr(start_addr),
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.refresh_finished(refresh_finished),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid),
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.dac_finished(dac_finished),
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.dac_arm(dac_arm),
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.dac_out(dac_out),
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.adc_finished(adc_finished),
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.adc_arm(adc_arm),
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.measurement(measurement)
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);
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endmodule
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