42 lines
830 B
Verilog
42 lines
830 B
Verilog
/* This module is a co-operative crossbar for the wires only. Each end
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* implements its own SPI master.
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*
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* This crossbar is entirely controlled by the kernel.
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*/
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module spi_crossbar #(
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parameter PORTS = 2,
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(
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input select[PORTS-1:0],
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output mosi,
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input miso,
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output sck,
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output ss,
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input mosi_ports[PORTS-1:0],
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output miso_ports[PORTS-1:0],
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input sck_ports[PORTS-1:0],
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input ss_ports[PORTS-1:0]
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);
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/* Avoid using for loops, they might not synthesize correctly.
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Do things the old, dumb way instead.
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*/
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always @(*) begin
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if (select[1]) begin
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mosi = mosi_ports[1];
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miso = miso_ports[1];
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sck = sck_ports[1];
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ss = ss_ports[1];
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end else begin
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/* Select zeroth slot by default. No latches. */
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mosi = mosi_ports[0];
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miso = miso_ports[0];
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sck = sck_ports[0];
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ss = ss_ports[0];
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end
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end
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endmodule
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