77 lines
1.2 KiB
Verilog
77 lines
1.2 KiB
Verilog
module dac_sim #(
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parameter POLARITY = 0,
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parameter PHASE = 1,
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parameter WID = 24,
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parameter DATA_WID = 20,
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parameter WID_LEN = 5
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) (
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input clk,
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input rst_L,
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output reg [DATA_WID-1:0] curset,
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input mosi,
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output miso,
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input sck,
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input ss_L,
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output err
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);
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wire [WID-1:0] from_master;
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reg [WID-1:0] to_master = 0;
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reg rdy = 1;
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wire spi_fin;
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reg [WID-4-1:0] ctrl_register = 0;
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always @ (posedge clk) begin
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if (!rst_L) begin
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curset <= 0;
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to_master <= 0;
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rdy <= 0;
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ctrl_register <= 0;
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end else if (spi_fin) begin
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rdy <= 0;
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case (from_master[WID-1:WID-4])
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4'b1001: begin
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to_master <= {4'b1001, curset};
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end
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4'b0001: begin
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curset <= from_master [DATA_WID-1:0];
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to_master <= 0;
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end
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4'b0010: begin
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ctrl_register <= to_master[WID-1-4:0];
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to_master <= 0;
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end
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4'b1010: begin
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to_master <= {4'b1010, ctrl_register};
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end
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default: to_master <= 0;
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endcase
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end else if (!rdy) begin
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rdy <= 1;
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end
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end
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spi_slave #(
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.WID(WID),
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.WID_LEN(WID_LEN),
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.POLARITY(POLARITY),
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.PHASE(PHASE)
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) spi (
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.clk(clk),
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.sck(sck),
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.ss_L(ss_L),
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.rst_L(rst_L),
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.miso(miso),
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.mosi(mosi),
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.from_master(from_master),
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.to_master(to_master),
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.finished(spi_fin),
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.rdy(rdy),
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.err(err)
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);
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endmodule
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`undefineall
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