Peter McGoron 0f86a60510 compile verilog		2023-04-03 15:29:20 -04:00
..
base	refactor soc.py base.v interface	2023-04-02 21:35:51 +00:00
control_loop	add yosys synth test for control loop	2023-03-20 13:57:42 -04:00
raster	arty.xdc for synth test	2023-03-20 13:58:35 -04:00
spi	move preprocessed generation to common makefile	2023-03-16 16:32:03 +00:00
waveform	compile verilog	2023-04-03 15:29:20 -04:00
Makefile	pass yosys	2023-03-15 17:08:55 -04:00
common.makefile	move preprocessed generation to common makefile	2023-03-16 16:32:03 +00:00
testbench.hpp	simulate waveform.v	2023-03-15 06:24:28 +00:00
util.hpp	test and simulate spi_switch	2023-03-14 15:42:41 +00:00