110 lines
2.6 KiB
Verilog
110 lines
2.6 KiB
Verilog
module bram_interface #(
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parameter WORD_WID = 24,
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parameter WORD_AMNT_WID = 11,
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/* This is the last INDEX, not the LENGTH of the word array. */
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parameter [WORD_AMNT_WID-1:0] WORD_AMNT = 2047,
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parameter RAM_WID = 32,
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parameter RAM_WORD_WID = 16,
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parameter RAM_WORD_INCR = 2
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) (
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input clk,
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/* autoapproach interface */
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output reg [WORD_WID-1:0] word,
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input word_next,
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output reg word_last,
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output reg word_ok,
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input word_rst,
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/* User interface */
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input refresh_start,
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input [RAM_WID-1:0] start_addr,
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output reg refresh_finished,
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/* RAM interface */
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output reg [RAM_WID-1:0] ram_dma_addr,
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input [RAM_WORD_WID-1:0] ram_word,
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output reg ram_read,
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input ram_valid
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);
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initial word = 0;
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initial word_last = 0;
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initial word_ok = 0;
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initial refresh_finished = 0;
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initial ram_dma_addr = 0;
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initial ram_read = 0;
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reg [WORD_WID-1:0] backing_buffer [WORD_AMNT:0];
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localparam WAIT_ON_REFRESH = 0;
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localparam READ_LOW_WORD = 1;
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localparam READ_HIGH_WORD = 2;
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localparam WAIT_ON_REFRESH_DEASSERT = 3;
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reg [1:0] refresh_state = 0;
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reg [WORD_AMNT_WID-1:0] word_cntr_refresh = 0;
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always @ (posedge clk) case (refresh_state)
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WAIT_ON_REFRESH: if (refresh_start) begin
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ram_dma_addr <= start_addr;
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refresh_state <= READ_LOW_WORD;
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word_cntr_refresh <= 0;
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end
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READ_LOW_WORD: if (!ram_read) begin
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ram_read <= 1;
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end else if (ram_valid) begin
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refresh_state <= READ_HIGH_WORD;
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ram_dma_addr <= ram_dma_addr + RAM_WORD_INCR;
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ram_read <= 0;
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backing_buffer[word_cntr_refresh][RAM_WORD_WID-1:0] <= ram_word;
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end
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READ_HIGH_WORD: if (!ram_read) begin
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ram_read <= 1;
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end else if (ram_valid) begin
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ram_dma_addr <= ram_dma_addr + RAM_WORD_INCR;
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ram_read <= 0;
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word_cntr_refresh <= word_cntr_refresh + 1;
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backing_buffer[word_cntr_refresh][WORD_WID-1:RAM_WORD_WID] <= ram_word[WORD_WID-RAM_WORD_WID-1:0];
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if (word_cntr_refresh == WORD_AMNT)
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refresh_state <= WAIT_ON_REFRESH_DEASSERT;
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else
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refresh_state <= READ_LOW_WORD;
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end
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WAIT_ON_REFRESH_DEASSERT: begin
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if (!refresh_start) begin
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refresh_finished <= 0;
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refresh_state <= WAIT_ON_REFRESH;
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end else begin
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refresh_finished <= 1;
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end
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end
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endcase
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reg [WORD_AMNT_WID-1:0] auto_cntr = 0;
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always @ (posedge clk) if (word_rst) begin
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auto_cntr <= 0;
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word_ok <= 0;
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word_last <= 0;
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word <= 0;
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end else if (word_next && !word_ok) begin
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if (refresh_state == WAIT_ON_REFRESH) begin
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word <= backing_buffer[auto_cntr];
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word_ok <= 1;
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if (auto_cntr == WORD_AMNT) begin
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auto_cntr <= 0;
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word_last <= 1;
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end else begin
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auto_cntr <= auto_cntr + 1;
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word_last <= 0;
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end
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end
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end else if (!word_next && word_ok) begin
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word_ok <= 0;
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end
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endmodule
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`undefineall
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