222 lines
9.9 KiB
Python
222 lines
9.9 KiB
Python
import textwrap
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class Descr:
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def __init__(self, name, blen, rwperm, num, descr):
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"""
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:param name: Name of the pin without numerical suffix.
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:param blen: Bit length of the pin.
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:param doc: Restructured text documentation of the register.
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:param num: The amount of registers of the same type.
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:param read_only: A string that must be either "read-only" or "write-write".
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"""
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self.name = name
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self.blen = blen
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self.doc = textwrap.dedent(descr)
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self.num =num
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self.rwperm = rwperm
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@classmethod
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def from_dict(cls, jsdict, name):
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return cls(name, jsdict[name]["len"], jsdict[name]["ro"], jsdict[name]["num"], jsdict[name]["doc"])
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def store_to_dict(self, d):
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d[self.name] = {
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"len": self.blen,
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"doc": self.doc,
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"num": self.num,
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"ro": ro
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}
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registers = [
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Descr("adc_sel", 3, "read-write", 8, """\
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Select which on-FPGA SPI master controls the ADC.
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Valid settings:
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* ``0``: ADC is controlled by MMIO registers.
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* ``0b10``: ADC is controlled by MMIO registers, but conversion is
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disabled. This is used to flush output from an out-of-sync ADC.
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* ``0b100``: ADC 0 only. ADC is controlled by control loop."""),
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Descr("adc_finished", 1, "read-only", 8, """\
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Signals that an ADC master has finished an SPI cycle.
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Values:
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* ``0``: MMIO master is either not armed or currently in a
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SPI transfer.
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* ``1``: MMIO master has finished.
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This flag is on only when ``adc_arm`` is high. The flag does not
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mean that data has been received successfully, only that the master
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has finished it's SPI transfer."""),
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Descr("adc_arm", 1, "read-write", 8, """\
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Start a DAC master SPI transfer.
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If ``adc_arm`` is raised from and the master is currently not in a SPI
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transfer, the SPI master will start an SPI transfer and write data
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into ``adc_recv_buf``.
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If ``adc_arm`` is raised while the master is in an SPI transfer,
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nothing changes.
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If ``adc_arm`` is lowered while the master is in an SPI transfer,
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nothing changes. The SPI cycle will continue to execute and it will
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continue to write data to ``adc_recv_buf``.
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If the SPI transfer finishes and ``adc_arm`` is still set to
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1, then ``adc_finished`` is raised to 1. If ``adc_arm`` is lowered
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in this state, then ``adc_finished`` is lowered.
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Linear Technologies ADCs must not have their SPI transfers
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interrupted. The transfer can be interrupted by
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1. Interrupt the signal physically (i.e. pulling out cable connecting
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the FPGA to the ADC)
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2. Reset of the ADC master
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3. Reset of the FPGA
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4. Switching ``adc_sel`` to the control loop
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If the ADC is interrupted then it will be in an unknown transfer
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state. To recover from an unknown transfer state, set ``adc_sel``
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to ``0b10`` and run a SPI transfer cycle. This will run the SPI
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clock and flush the ADC buffer. The only other way is to power-cycle
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the ADC.
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If ``adc_sel`` is not set to 0 then the transfer will proceed
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as normal, but no data will be received from the ADC."""),
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Descr("adc_recv_buf", 18, "read-only", 8, """\
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ADC Master receive buffer.
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This buffer is stable if there is no ADC transfer caused by ``adc_arm``
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is in process.
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This register only changes if an SPI transfer is triggered by the MMIO
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registers. SPI transfers by other masters will not affect this register.
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buffer."""),
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Descr("dac_sel", 2, "read-write", 8, """\
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Select which on-FPGA SPI master controls the DAC.
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Valid settings:
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* ``0``: DAC is controlled by MMIO registers.
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* ``0b10``: DAC 0 only. DAC is controlled by control loop."""),
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Descr("dac_finished", 1, "read-only", 8, """\
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Signals that the DAC master has finished transmitting data.
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Values:
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* ``0``: MMIO master is either not armed or currently in a
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SPI transfer.
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* ``1``: MMIO master has finished transmitting.
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This flag is on only when ``dac_arm`` is high. The flag does not
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mean that data has been received or transmitted successfully, only that
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the master has finished it's SPI transfer."""),
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Descr("dac_arm", 1, "read-write", 8, """\
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Start a DAC master SPI transfer.
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If ``dac_arm`` is raised from and the master is currently not in a SPI
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transfer, the SPI master reads from the ``dac_send_buf`` register and sends
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it over the wire to the DAC, while reading data from the DAC into
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``dac_recv_buf``.
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If ``dac_arm`` is raised while the master is in an SPI transfer,
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nothing changes.
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If ``dac_arm`` is lowered while the master is in an SPI transfer,
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nothing changes. The SPI cycle will continue to execute and it will
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continue to write data to ``dac_recv_buf``.
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If the SPI transfer finishes and ``dac_arm`` is still set to
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1, then ``dac_finished`` is raised to 1. If ``dac_arm`` is lowered
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in this state, then ``dac_finished`` is lowered.
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Analog Devices DACs can have their SPI transfers interrupted without
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issue. However it is currently not possible to interrupt SPI transfers
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in software without resetting the entire device.
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If ``dac_sel`` is set to another master then the transfer will proceed
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as normal, but no data will be sent to or received from the DAC."""),
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Descr("dac_recv_buf", 24, "read-only", 8, """\
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DAC master receive buffer.
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This buffer is stable if there is no DAC transfer caused by ``dac_arm``
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is in process.
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This register only changes if an SPI transfer is triggered by the MMIO
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registers. SPI transfers by other masters will not affect this register.
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buffer."""),
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Descr("dac_send_buf", 24, "read-write", 8, """\
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DAC master send buffer.
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Fill this buffer with a 24 bit Analog Devices DAC command. Updating
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this buffer does not start an SPI transfer. To send data to the DAC,
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fill this buffer and raise ``dac_arm``.
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The DAC copies this buffer into an internal register when writing data.
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Modifying this buffer during a transfer does not disrupt an in-process
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transfer."""),
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Descr("cl_assert_change", 1, "read-write", 1, """\
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Flush parameter changes to control loop.
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When this bit is raised from low to high, this signals the control
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loop that it should read in new values from the MMIO registers.
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While the bit is raised high, the control loop will read the constants
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at most once.
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When this bit is raised from high to low before ``cl_change_made``
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is asserted by the control loop, nothing happens."""),
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Descr("cl_change_made", 1, "read-only", 1, """\
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Signal from the control loop that the parameters have been applied.
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This signal goes high only while ``cl_assert_change`` is high. No
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change will be applied afterwards while both are high."""),
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Descr("cl_in_loop", 1, "read-only", 1, """\
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This bit is high if the control loop is running."""),
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Descr("cl_run_loop_in", 1, "read-write", 1, """\
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Set this bit high to start the control loop."""),
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Descr("cl_setpt_in", 18, "read-write", 1, """\
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Setpoint of the control loop.
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This is a twos-complement number in ADC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_P_in", 64, "read-write", 1, """\
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Proportional parameter of the control loop.
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This is a twos-complement fixed point number with 21 whole
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bits and 43 fractional bits. This is applied to the error
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in DAC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_I_in", 64, "read-write", 1, """\
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Integral parameter of the control loop.
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This is a twos-complement fixed point number with 21 whole
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bits and 43 fractional bits. This is applied to the error
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in DAC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_delay_in", 16, "read-write", 1, """\
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Delay parameter of the loop.
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This is an unsigned number denoting the number of cycles
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the loop should wait between loop executions.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_cycle_count", 18, "read-only", 1, """\
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Delay parameter of the loop.
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This is an unsigned number denoting the number of cycles
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the loop should wait between loop executions."""),
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Descr("cl_z_pos", 20, "read-only", 1, """\
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Control loop DAC Z position.
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"""),
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Descr("cl_z_measured", 18, "read-only", 1, """\
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Control loop ADC Z position.
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"""),
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]
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