346 lines
9.6 KiB
Verilog
346 lines
9.6 KiB
Verilog
/* Copyright 2023 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*/
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/* Raster scanner. This module sweeps two DACs (the X and Y piezos)
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* across a box, where the X and Y axes may be at an angle. After
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* a single step, the ADCs connected to the raster scanner are
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* activated, with each value read into system memory (see ram_shim).
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* The kernel then reads these values and sends them to the controller
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* over ethernet.
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*/
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`include "raster_cmds.vh"
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`timescale 10ns/10ns
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module raster #(
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parameter DAC_WAIT_BETWEEN_CMD = 10
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) (
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input clk,
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`ifdef VERILATOR
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output is_running,
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`endif
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/* Kernel interface. */
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input [`RASTER_CMD_WID-1:0] kernel_cmd,
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/* verilator lint_off UNUSEDSIGNAL */
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input [`RASTER_DATA_WID-1:0] kernel_data_in,
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/* verilator lint_on UNUSEDSIGNAL */
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output reg [`RASTER_DATA_WID-1:0] kernel_data_out,
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input kernel_ready,
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output reg kernel_finished,
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/* X and Y DAC piezos */
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output x_arm,
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output [`DAC_WID-1:0] x_to_dac,
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/* verilator lint_off UNUSED */
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input [`DAC_WID-1:0] x_from_dac,
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/* verilator lint_on UNUSED */
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input x_finished,
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output y_arm,
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output [`DAC_WID-1:0] y_to_dac,
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/* verilator lint_off UNUSED */
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input [`DAC_WID-1:0] y_from_dac,
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/* verilator lint_on UNUSED */
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input y_finished,
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/* Connections to all possible ADCs. These are connected to SPI masters
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* and they will automatically extend ADC value lengths to their highest
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* values. */
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output reg [`ADCNUM-1:0] adc_arm,
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/* Yosys does not support input arrays. */
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input [`ADCNUM*`MAX_ADC_DATA_WID-1:0] adc_data,
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input [`ADCNUM-1:0] adc_finished,
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/* RAM DMA. This is generally not directly connected to the
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* DMA IP. A shim is used in order to write multiple words
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* to memory. */
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output reg [`MAX_ADC_DATA_WID-1:0] data,
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output reg mem_commit,
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input mem_finished
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);
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/* During a scan, some of the ADCs will be scanned, but some will not.
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* The data are packed in such a way so that the most significant
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* word will contain the highest enabled ADC number, and the least
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* significant word will contain the lowest enabled ADC number (and so
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* on in between).
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*
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* There's not a good way to precalculate this so instead the check
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* is done at each "send" stage.
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*/
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/* State machine:
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┏━━━━ WAIT ON ARM
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↑ ↓ (arm -> 1)
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┃ REQUEST DAC VALUES
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┃ ↓ (when x and y values are requested)
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┃ OBTAIN DAC VALUES
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┃ ↓ (when x and y values are measured)
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┃ ┏━LOOP FORWARD WITHOUT MEASUREMENT
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┃ ↑ ↓ (when enough steps are taken)
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┃ ┃ GET ADC VALUES
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┃ ┃ ↓ (when all ADC values are obtained)
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┃ ┃ SEND THROUGH FIFO
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┃ ┃ ↓ (when finished)
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┃ ┏━┫ ┃
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┃ ↑ ┗━━━←━┫
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┃ ┃ ┃ (when at the end of a line)
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┃ ┃ ┃
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┃ ┃ ┏━LOOP BACKWARD WITHOUT MEASUREMENT
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┃ ┃ ↑ ↓ (when enough steps are taken)
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┃ ┃ ┃ GET ADC VALUES, BACKWARDS MEASUREMENT
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┃ ┃ ┃ ↓ (when all ADC values are obtained)
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┃ ┃ ┃ SEND THROUGH FIFO, BACKWARDS MEASUREMENT
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┃ ┃ ┃ ↓ (when finished)
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┃ ┃ ┃ ┃
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┃ ┃ ┗━━━←━┫
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┃ ┃ ↓
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┃ ┗━━━━━━━┫
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┃ ↓ (when the image is finished)
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┃ ┃
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┃ WAIT FOR ARM DEASSERT
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┃ ↓ (when arm = 0)
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┗━━━━━━━━━┛
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*/
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localparam WAIT_ON_ARM = 0;
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localparam REQUEST_DAC_VALUES = 1;
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localparam GET_DAC_VALUES = 2;
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localparam WAIT_ADVANCE = 3;
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localparam MEASURE = 4;
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localparam SCAN_ADC_VALUES = 5;
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localparam ADVANCE_DAC_WRITE = 6;
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localparam NEXT_LINE = 7;
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localparam WAIT_ON_ARM_DEASSERT = 8;
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localparam STATE_WID = 4;
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/********** Loop State ***********/
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reg [STATE_WID-1:0] state = WAIT_ON_ARM;
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reg [`SAMPLEWID-1:0] sample = 0;
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reg [`SAMPLEWID-1:0] line = 0;
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reg [`TIMERWID-1:0] counter = 0;
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reg signed [`DAC_DATA_WID-1:0] x_val = 0;
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reg signed [`DAC_DATA_WID-1:0] y_val = 0;
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/* Buffer to store all measured ADC values. This
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* is shifted until it is all zeros to determine
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* which ADC values should be read off.
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*/
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reg [`ADCNUM-1:0] adc_used_tmp = 0;
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reg [`ADCNUM*`MAX_ADC_DATA_WID-1:0] adc_data_tmp = 0;
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/********** Loop Parameters *************/
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reg [`ADCNUM-1:0] adc_used = 0;
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reg is_reverse = 0;
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reg arm = 0;
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reg running = 0;
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`ifdef VERILATOR
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assign is_running = running;
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`endif
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reg signed [`DAC_DATA_WID-1:0] dx = 0;
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reg signed [`DAC_DATA_WID-1:0] dy = 0;
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reg [`TIMERWID-1:0] settle_time = 0;
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reg [`SAMPLEWID-1:0] max_samples = 0;
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reg [`SAMPLEWID-1:0] max_lines = 0;
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/********** Control Interface ************
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* This code assumes that RASTER_DATA_WID is greater than all registers.
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* If a register is equal to the length, omit zero extension.
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*
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* This uses a macro since each register is exactly the same code, just
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* with different length. The arm register is special: it can be adjusted
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* while the loop is running (in order to terminate the scan), but
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* otherwise each register can only be modified when the loop is not
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* running.
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*/
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// Generates code to handle read requests from the kernel.
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`define generate_register_read(code, width, register) \
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code: begin \
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kernel_data_out[(width)-1:0] <= register; \
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kernel_data_out[`RASTER_DATA_WID-1:(width)] <= 0; \
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kernel_finished <= 1; \
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end
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// Generates code to handle write requests from the kernel.
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`define generate_register(code, width, register) \
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`generate_register_read(code, width, register) \
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code | `RASTER_WRITE_BIT: \
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if (!running || (code) == `RASTER_ARM) begin \
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register <= kernel_data_in[(width)-1:0]; \
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kernel_finished <= 1; \
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end
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always @ (posedge clk) begin
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if (!kernel_ready) kernel_finished <= 0;
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else if (kernel_ready) begin case (kernel_cmd)
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`generate_register(`RASTER_MAX_SAMPLES, `SAMPLEWID, max_samples)
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`generate_register(`RASTER_MAX_LINES, `SAMPLEWID, max_lines)
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`generate_register(`RASTER_SETTLE_TIME, `TIMERWID, settle_time)
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`generate_register(`RASTER_DX, `DAC_DATA_WID, dx)
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`generate_register(`RASTER_DY, `DAC_DATA_WID, dy)
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`generate_register(`RASTER_USED_ADCS, `ADCNUM, adc_used)
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`generate_register(`RASTER_ARM, 1, arm)
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`generate_register_read(`RASTER_RUNNING, 1, running)
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`ifdef VERILATOR
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default: $error("unknown kernel message");
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`endif
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endcase end
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end
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`undef generate_register_read
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`undef generate_register
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task check_arm();
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if (!arm) begin
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state <= WAIT_ON_ARM;
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running <= 0;
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end
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endtask
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`ifdef VERILATOR
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task check_deassert_dac_arm();
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if (x_arm) $error("x_arm asserted");
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if (y_arm) $error("y_arm asserted");
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endtask
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`define CHECK_DAC_ARM check_deassert_dac_arm();
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`else
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`define CHECK_DAC_ARM
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`endif
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always @ (posedge clk) begin
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case (state)
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WAIT_ON_ARM: if (arm) begin
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running <= 1;
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is_reverse <= 0;
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sample <= 0;
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line <= 0;
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x_to_dac <= {4'b1001, 20'b0};
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y_to_dac <= {4'b1001, 20'b0};
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x_arm <= 1;
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y_arm <= 1;
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adc_arm <= 0;
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state <= REQUEST_DAC_VALUES;
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end
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REQUEST_DAC_VALUES: if (x_finished && y_finished) begin
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x_to_dac <= 0;
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y_to_dac <= 0;
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x_arm <= 0;
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y_arm <= 0;
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state <= GET_DAC_VALUES;
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counter <= 0;
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end
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GET_DAC_VALUES: if (counter < DAC_WAIT_BETWEEN_CMD) begin
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`CHECK_DAC_ARM
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counter <= counter + 1;
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check_arm();
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end else if (!x_arm || !y_arm) begin
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x_arm <= 1;
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y_arm <= 1;
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end else if (x_finished && y_finished) begin
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x_val <= x_from_dac[`DAC_DATA_WID-1:0];
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y_val <= y_from_dac[`DAC_DATA_WID-1:0];
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x_arm <= 0;
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y_arm <= 0;
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counter <= 0;
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state <= WAIT_ADVANCE;
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end
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WAIT_ADVANCE: if (counter < settle_time) begin
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check_arm();
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counter <= counter + 1;
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`CHECK_DAC_ARM
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end else begin
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`CHECK_DAC_ARM
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adc_arm <= adc_used;
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adc_used_tmp <= adc_used;
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state <= MEASURE;
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end
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MEASURE: if (adc_finished == adc_arm) begin
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`CHECK_DAC_ARM
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adc_arm <= 0;
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adc_data_tmp <= adc_data;
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state <= SCAN_ADC_VALUES;
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counter <= 0;
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end
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SCAN_ADC_VALUES: if (adc_used_tmp == 0 && !mem_commit) begin
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`CHECK_DAC_ARM
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if (sample == max_samples-1) begin
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dx <= ~dx + 1;
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dy <= ~dy + 1;
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if (is_reverse) begin
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state <= NEXT_LINE;
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end else begin
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state <= ADVANCE_DAC_WRITE;
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end
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is_reverse <= !is_reverse;
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sample <= 0;
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end else begin
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sample <= sample + 1;
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state <= ADVANCE_DAC_WRITE;
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end
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end else if (mem_finished) begin
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`CHECK_DAC_ARM
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state <= SCAN_ADC_VALUES;
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mem_commit <= 0;
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end else begin
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`CHECK_DAC_ARM
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adc_used_tmp <= adc_used_tmp << 1;
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adc_data_tmp <= adc_data_tmp << `MAX_ADC_DATA_WID;
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if (adc_used_tmp[`ADCNUM-1]) begin
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data <= adc_data_tmp[`ADCNUM*`MAX_ADC_DATA_WID-1:(`ADCNUM-1)*`MAX_ADC_DATA_WID];
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mem_commit <= 1;
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end
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end
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ADVANCE_DAC_WRITE: if (!x_arm || !y_arm) begin
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x_val <= x_val + dx;
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y_val <= y_val + dy;
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x_to_dac <= {4'b0001, x_val + dx};
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y_to_dac <= {4'b0001, y_val + dy};
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x_arm <= 1;
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y_arm <= 1;
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end else if (x_finished && y_finished) begin
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counter <= 0;
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state <= WAIT_ADVANCE;
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x_arm <= 0;
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y_arm <= 0;
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end
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NEXT_LINE: if (!x_arm || !y_arm) begin
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if (line == max_lines-1) begin
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state <= WAIT_ON_ARM_DEASSERT;
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end else begin
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sample <= 0;
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/* rotation of (dx,dy) by 90° -> (dy, -dx) */
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x_val <= x_val + dy;
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x_to_dac <= {4'b0001, x_val + dy};
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x_arm <= 1;
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y_val <= y_val - dx;
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y_to_dac <= {4'b0001, y_val - dx};
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y_arm <= 1;
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line <= line + 1;
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end
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end else if (x_finished && y_finished) begin
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counter <= 0;
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state <= WAIT_ADVANCE;
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x_arm <= 0;
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y_arm <= 0;
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end
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WAIT_ON_ARM_DEASSERT: if (!arm) begin
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state <= WAIT_ON_ARM;
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end else begin
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running <= 0;
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end
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endcase
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end
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endmodule
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`undefineall
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