302 lines
13 KiB
Python
302 lines
13 KiB
Python
"""
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##########################################################################
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# Portions of this file incorporate code licensed under the
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# BSD 2-Clause License.
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# BSD 2-Clause License
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#
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# Copyright (c) Copyright 2012-2022 Enjoy-Digital.
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# Copyright (c) Copyright 2012-2022 / LiteX-Hub community.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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##########################################################################
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# Copyright 2023 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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"""
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# There is nothing fundamental about the Arty A7(35|100)T to this
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# design, but another eval board will require some porting.
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from migen import *
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import litex_boards.platforms.digilent_arty as board_spec
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.integration.builder import Builder
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from litex.build.generic_platform import IOStandard, Pins, Subsignal
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from litedram.frontend.dma import LiteDRAMDMAReader
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from liteeth.phy.mii import LiteEthPHYMII
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import mmio_descr
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"""
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Keep this diagram up to date! This is the wiring diagram from the ADC to
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the named Verilog pins.
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Refer to `A7-constraints.xdc` for pin names.
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DAC: SS MOSI MISO SCK
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0: 1 2 3 4 (PMOD A top, right to left)
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1: 1 2 3 4 (PMOD A bottom, right to left)
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2: 1 2 3 4 (PMOD B top, right to left)
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3: 0 1 2 3 (Analog header)
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4: 0 1 2 3 (PMOD C top, right to left)
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5: 4 5 6 8 (Analog header)
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6: 1 2 3 4 (PMOD D top, right to left)
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7: 1 2 3 4 (PMOD D bottom, right to left)
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Outer chip header (C=CONV, K=SCK, D=SDO, XX=not connected)
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
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C4 K4 D4 C5 K5 D5 XX XX C6 K6 D6 C7 K7 D7 XX XX
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C0 K0 D0 C1 K1 D1 XX XX C2 K2 D2 C3 K3 D3
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0 1 2 3 4 5 6 7 8 9 10 11 12 13
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The `io` list maps hardware pins to names used by the SoC
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generator. These pins are then connected to Verilog modules.
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If there is more than one pin in the Pins string, the resulting
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name will be a vector of pins.
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"""
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io = [
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("differntial_output_low", 0, Pins("J17 J18 K15 J15 U14 V14 T13 U13 B6 E5 A3"), IOStandard("LVCMOS33")),
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("dac_ss_L", 0, Pins("G13 D13 E15 F5 U12 D7 D4 E2"), IOStandard("LVCMOS33")),
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("dac_mosi", 0, Pins("B11 B18 E16 D8 V12 D5 D3 D2"), IOStandard("LVCMOS33")),
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("dac_miso", 0, Pins("A11 A18 D15 C7 V10 B7 F4 H2"), IOStandard("LVCMOS33")),
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("dac_sck", 0, Pins("D12 K16 C15 E7 V11 E6 F3 G2"), IOStandard("LVCMOS33")),
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("adc_conv", 0, Pins("V15 T11 N15 U18 U11 R10 R16 U17"), IOStandard("LVCMOS33")),
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("adc_sck", 0, Pins("U16 R12 M16 R17 V16 R11 N16 T18"), IOStandard("LVCMOS33")),
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("adc_sdo", 0, Pins("P14 T14 V17 P17 M13 R13 N14 R18"), IOStandard("LVCMOS33")),
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("module_reset", 0, Pins("D9"), IOStandard("LVCMOS33")),
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("test_clock", 0, Pins("P18"), IOStandard("LVCMOS33"))
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]
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# TODO: Assign widths to ADCs here using parameters
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class Base(Module, AutoCSR):
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""" The subclass AutoCSR will automatically make CSRs related
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to this class when those CSRs are attributes (i.e. accessed by
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`self.csr_name`) of instances of this class. (CSRs are MMIO,
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they are NOT RISC-V CSRs!)
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Since there are a lot of input and output wires, the CSRs are
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assigned using `setattr()`.
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CSRs are for input wires (`CSRStorage`) or output wires
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(`CSRStatus`). The first argument to the CSR constructor is
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the amount of bits the CSR takes. The `name` keyword argument
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is required since the constructor needs the name of the attribute.
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The `description` keyword is used for documentation.
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In LiteX, modules in separate Verilog files are instantiated as
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self.specials += Instance(
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"module_name",
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PARAMETER_NAME=value,
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i_input = input_port,
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o_output = output_port,
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...
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)
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Since the "base" module has a bunch of repeated input and output
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pins that have to be connected to CSRs, the LiteX wrapper uses
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keyword arguments to pass all the arguments.
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"""
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def _make_csr(self, reg, num=None):
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""" Add a CSR for a pin `f"{name}_{num}".`
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:param name: Name of the MMIO register without prefixes or numerical
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suffix.
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:param num: Numerical suffix of this MMIO register. This is the only
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parameter that should change when adding multiple CSRs of the same
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name.
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"""
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name = reg.name
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if num is not None:
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name = f"{name}_{num}"
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if reg.rwperm == "read-only":
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csrclass = CSRStatus
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else:
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csrclass = CSRStorage
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csr = csrclass(reg.blen, name=name, description=None)
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setattr(self, name, csr)
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if csrclass is CSRStorage:
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self.kwargs[f'i_{name}'] = csr.storage
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elif csrclass is CSRStatus:
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self.kwargs[f'o_{name}'] = csr.status
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else:
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raise Exception(f"Unknown class {csrclass}")
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def __init__(self, clk, sdram, platform):
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self.kwargs = {}
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for reg in mmio_descr.registers:
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if reg.num > 1:
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for i in range(0,reg.num):
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self._make_csr(reg,i)
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else:
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self._make_csr(reg)
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self.kwargs["i_clk"] = clk
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self.kwargs["i_rst_L"] = ~platform.request("module_reset")
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self.kwargs["i_dac_miso"] = platform.request("dac_miso")
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self.kwargs["o_dac_mosi"] = platform.request("dac_mosi")
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self.kwargs["o_dac_sck"] = platform.request("dac_sck")
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self.kwargs["o_dac_ss_L"] = platform.request("dac_ss_L")
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self.kwargs["o_adc_conv"] = platform.request("adc_conv")
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self.kwargs["i_adc_sdo"] = platform.request("adc_sdo")
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self.kwargs["o_adc_sck"] = platform.request("adc_sck")
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self.kwargs["o_set_low"] = platform.request("differntial_output_low")
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self.specials += Instance("base", **self.kwargs)
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# Clock and Reset Generator
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# I don't know how this works, I only know that it does.
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram, rst_pin):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~rst_pin if rst_pin is not None else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class UpsilonSoC(SoCCore):
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def __init__(self, variant):
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sys_clk_freq = int(100e6)
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platform = board_spec.Platform(variant=variant, toolchain="f4pga")
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rst = platform.request("cpu_reset")
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self.submodules.crg = _CRG(platform, sys_clk_freq, True, rst)
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"""
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These source files need to be sorted so that modules
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that rely on another module come later. For instance,
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`control_loop` depends on `control_loop_math`, so
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control_loop_math.v comes before control_loop.v
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If you want to add a new verilog file to the design, look at the
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modules that it refers to and place it the files with those modules.
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Since Yosys doesn't support modern Verilog, only put preprocessed
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(if applicable) files here.
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"""
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platform.add_source("rtl/spi/spi_switch_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_no_write_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_no_read_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_ss_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_ss_no_write_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_ss_no_read_preprocessed.v")
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platform.add_source("rtl/control_loop/sign_extend.v")
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platform.add_source("rtl/control_loop/intsat.v")
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platform.add_source("rtl/control_loop/boothmul_preprocessed.v")
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platform.add_source("rtl/control_loop/control_loop_math.v")
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platform.add_source("rtl/control_loop/control_loop.v")
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# platform.add_source("rtl/waveform/bram_interface_preprocessed.v")
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# platform.add_source("rtl/waveform/waveform_preprocessed.v")
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platform.add_source("rtl/base/base.v")
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# SoCCore does not have sane defaults (no integrated rom)
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SoCCore.__init__(self,
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clk_freq=sys_clk_freq,
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toolchain="symbiflow",
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platform = platform,
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bus_standard = "wishbone",
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ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr - Upsilon",
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bus_data_width = 32,
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bus_address_width = 32,
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bus_timeout = int(1e6),
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cpu_type = "vexriscv_smp",
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cpu_count = 1,
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cpu_variant="linux",
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integrated_rom_size=0x20000,
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integrated_sram_size = 0x2000,
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csr_data_width=32,
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csr_address_width=14,
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csr_paging=0x800,
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csr_ordering="big",
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local_ip='192.168.1.50',
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remote_ip='192.168.1.100',
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timer_uptime = True)
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# This initializes the connection to the physical DRAM interface.
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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# Synchronous dynamic ram. This is what controls all access to RAM.
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# This houses the "crossbar", which negotiates all RAM accesses to different
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# modules, including the verilog interfaces (waveforms etc.)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 8192
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)
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, dynamic_ip=True)
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platform.add_extension(io)
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self.submodules.base = Base(ClockSignal(), self.sdram, platform)
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def main():
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soc =UpsilonSoC("a7-100")
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builder = Builder(soc, csr_json="csr.json", compile_software=True)
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builder.build()
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if __name__ == "__main__":
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main()
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