120 lines
4.2 KiB
Python
120 lines
4.2 KiB
Python
# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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from migen import *
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from litex.soc.interconnect.wishbone import Decoder, Interface
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from litex.gen import LiteXModule
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from util import *
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"""
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LiteX has an automatic Wishbone bus generator that has a lot of quality of life
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features, like overlap checking, relocation, multiple masters, etc.
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It doesn't work when the main SoC bus is also using the bus generator, so this
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module implements a basic Wishbone bus generator. All locations have to be
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added manually and there is no sanity checking.
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"""
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class BasicRegion:
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""" Simple class for storing a RAM region. """
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def __init__(self, origin, size, bus=None, registers=None):
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"""
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:param origin: Positive integer denoting the start location
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of the memory region.
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:param size: Size of the memory region. This must be of the form
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(2**N - 1).
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:param bus: Instance of a wishbone bus interface.
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:param registers: Dictionary where keys are names of addressable
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areas in the region, values have "offset" and "width", and
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optionally other parameters that help with describing the
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subregion.
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"""
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self.origin = origin
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self.size = size
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self.bus = bus
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self.registers = registers
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def decoder(self):
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"""
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Wishbone decoder generator. The decoder looks at the high
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bits of the address to check what bits are passed to the
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slave device.
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Examples:
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Location 0x10000 has 0xFFFF of address space.
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origin = 0x10000, rightbits = 16.
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Location 0x10000 has 0xFFF of address space.
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origin = 0x10000, rightbits = 12.
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Location 0x100000 has 0x1F of address space.
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origin = 0x100000, rightbits = 5.
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"""
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rightbits = minbits(self.size-1)
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print(self.origin, self.origin >> rightbits)
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return lambda addr: addr[rightbits:32] == (self.origin >> rightbits)
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def to_dict(self):
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return {"origin" : self.origin, "width": self.size, "registers": self.registers}
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def __str__(self):
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return str(self.to_dict())
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class MemoryMap(LiteXModule):
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""" Stores the memory map of an embedded core. """
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def __init__(self, masterbus):
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self.regions = {}
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self.masterbus = masterbus
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def add_region(self, name, region):
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assert name not in self.regions
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self.regions[name] = region
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def dump_mmap(self, jsonfile):
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with open(jsonfile, 'wt') as f:
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import json
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json.dump({k : self.regions[k].to_dict() for k in self.regions}, f)
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def adapt(self, target_bus):
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"""
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When a slave is "word" addressed (like SRAM), it accepts an index
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into a array with 32-bit elements. It DOES NOT accept a byte index.
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When a byte-addressed master (like the CPU) interacts with a word
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addressed slave, there must be an adapter in between that converts
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between the two.
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PicoRV32 will read the word that contains a byte/halfword and
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extract the word from it (see code assigning mem_rdata_word).
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"""
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assert target_bus.addressing in ["byte", "word"]
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if target_bus.addressing == "byte":
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return target_bus
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adapter = Interface(data_width=32, address_width=32, addressing="byte")
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self.comb += [
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target_bus.adr.eq(adapter.adr >> 2),
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target_bus.dat_w.eq(adapter.dat_w),
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target_bus.we.eq(adapter.we),
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target_bus.sel.eq(adapter.sel),
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target_bus.cyc.eq(adapter.cyc),
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target_bus.stb.eq(adapter.stb),
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target_bus.cti.eq(adapter.cti),
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target_bus.bte.eq(adapter.bte),
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adapter.ack.eq(target_bus.ack),
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adapter.dat_r.eq(target_bus.dat_r),
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]
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return adapter
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def do_finalize(self):
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slaves = [(self.regions[n].decoder(), self.adapt(self.regions[n].bus))
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for n in self.regions]
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self.submodules.decoder = Decoder(self.masterbus, slaves, register=True)
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