414 lines
17 KiB
Python
414 lines
17 KiB
Python
"""
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##########################################################################
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# Portions of this file incorporate code licensed under the
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# BSD 2-Clause License.
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#
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# Copyright (c) 2014-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# BSD 2-Clause License
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#
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# Copyright (c) Copyright 2012-2022 Enjoy-Digital.
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# Copyright (c) Copyright 2012-2022 / LiteX-Hub community.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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##########################################################################
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# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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"""
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# There is nothing fundamental about the Arty A7(35|100)T to this
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# design, but another eval board will require some porting.
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from migen import *
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import litex_boards.platforms.digilent_arty as board_spec
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from litex.soc.integration.builder import Builder
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from litex.build.generic_platform import IOStandard, Pins, Subsignal
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.soc import SoCRegion, SoCBusHandler, SoCIORegion
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litex.soc.interconnect.wishbone import Interface, SRAM, Decoder
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from litedram.frontend.dma import LiteDRAMDMAReader
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from liteeth.phy.mii import LiteEthPHYMII
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from util import *
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from swic import *
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from extio import *
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from region import BasicRegion
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import json
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"""
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Keep this diagram up to date! This is the wiring diagram from the ADC to
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the named Verilog pins.
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Refer to `A7-constraints.xdc` for pin names.
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DAC: SS MOSI MISO SCK
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0: 1 2 3 4 (PMOD A top, right to left)
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1: 1 2 3 4 (PMOD A bottom, right to left)
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2: 1 2 3 4 (PMOD B top, right to left)
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3: 0 1 2 3 (Analog header)
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4: 0 1 2 3 (PMOD C top, right to left)
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5: 4 5 6 8 (Analog header)
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6: 1 2 3 4 (PMOD D top, right to left)
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7: 1 2 3 4 (PMOD D bottom, right to left)
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Outer chip header (C=CONV, K=SCK, D=SDO, XX=not connected)
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
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C4 K4 D4 C5 K5 D5 XX XX C6 K6 D6 C7 K7 D7 XX XX
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C0 K0 D0 C1 K1 D1 XX XX C2 K2 D2 C3 K3 D3
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0 1 2 3 4 5 6 7 8 9 10 11 12 13
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The `io` list maps hardware pins to names used by the SoC
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generator. These pins are then connected to Verilog modules.
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If there is more than one pin in the Pins string, the resulting
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name will be a vector of pins.
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TODO: generate declaratively from constraints file.
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"""
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io = [
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# ("differntial_output_low", 0, Pins("J17 J18 K15 J15 U14 V14 T13 U13 B6 E5 A3"), IOStandard("LVCMOS33")),
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("dac_ss_L_0", 0, Pins("G13"), IOStandard("LVCMOS33")),
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("dac_mosi_0", 0, Pins("B11"), IOStandard("LVCMOS33")),
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("dac_miso_0", 0, Pins("A11"), IOStandard("LVCMOS33")),
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("dac_sck_0", 0, Pins("D12"), IOStandard("LVCMOS33")),
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# ("dac_ss_L", 0, Pins("G13 D13 E15 F5 U12 D7 D4 E2"), IOStandard("LVCMOS33")),
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# ("dac_mosi", 0, Pins("B11 B18 E16 D8 V12 D5 D3 D2"), IOStandard("LVCMOS33")),
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# ("dac_miso", 0, Pins("A11 A18 D15 C7 V10 B7 F4 H2"), IOStandard("LVCMOS33")),
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# ("dac_sck", 0, Pins("D12 K16 C15 E7 V11 E6 F3 G2"), IOStandard("LVCMOS33")),
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("adc_conv_0", 0, Pins("V15"), IOStandard("LVCMOS33")),
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("adc_sck_0", 0, Pins("U16"), IOStandard("LVCMOS33")),
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("adc_sdo_0", 0, Pins("P14"), IOStandard("LVCMOS33")),
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# ("adc_conv", 0, Pins("V15 T11 N15 U18 U11 R10 R16 U17"), IOStandard("LVCMOS33")),
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# ("adc_sck", 0, Pins("U16 R12 M16 R17 V16 R11 N16 T18"), IOStandard("LVCMOS33")),
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# ("adc_sdo", 0, Pins("P14 T14 V17 P17 M13 R13 N14 R18"), IOStandard("LVCMOS33")),
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("module_reset", 0, Pins("D9"), IOStandard("LVCMOS33")),
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# ("test_clock", 0, Pins("P18"), IOStandard("LVCMOS33"))
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]
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# Clock and Reset Generator
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# I don't know how this works, I only know that it does.
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram, rst_pin):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~rst_pin if rst_pin is not None else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class UpsilonSoC(SoCCore):
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def add_ip(self, ip_str, ip_name):
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# The IP of the FPGA and the IP of the TFTP server are stored as
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# "constants" which turn into preprocessor defines.
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# They are IPv4 addresses that are split into octets. So the local
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# ip is LOCALIP1, LOCALIP2, etc.
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for seg_num, ip_byte in enumerate(ip_str.split('.'),start=1):
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self.add_constant(f"{ip_name}{seg_num}", int(ip_byte))
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def add_slave_with_registers(self, name, bus, region, registers):
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""" Add a bus slave, and also add its registers to the subregions
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dictionary. """
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self.bus.add_slave(name, bus, region)
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self.soc_subregions[name] = registers
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def add_blockram(self, name, size, connect_now=True):
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""" Add a blockram module to the system.
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:param connect_now: Connect the block ram directly to the SoC.
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You will probably never need this, since this just adds
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more ram to the main CPU which already has 256 MiB of RAM.
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Only useful for testing to see if the Blockram works by poking
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it directly from the main CPU.
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"""
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mod = SRAM(size)
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self.add_module(name, mod)
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if connect_now:
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self.bus.add_slave(name, mod.bus,
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SoCRegion(origin=None, size=size, cached=True))
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return mod
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def add_preemptive_interface(self, name, size, slave):
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""" Add a preemptive interface with "size" connected to the slave's bus. """
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mod = PreemptiveInterface(size, slave)
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self.add_module(name, mod)
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return mod
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def add_picorv32(self, name, size=0x1000, origin=0x10000):
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# Add PicoRV32 core
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pico = PicoRV32(name, origin, origin+0x10)
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self.add_module(name, pico)
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# Attach the register region to the main CPU.
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self.add_slave_with_registers(name + "_dbg_reg", pico.debug_reg_read.bus,
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SoCRegion(origin=None, size=pico.debug_reg_read.width, cached=False),
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pico.debug_reg_read.public_registers)
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# Add a Block RAM for the PicoRV32 toexecute from.
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ram = self.add_blockram(name + "_ram", size=size, connect_now=False)
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# Control access to the Block RAM from the main CPU.
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ram_iface = self.add_preemptive_interface(name + "ram_iface", 2, ram)
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# Allow access from the PicoRV32 to the Block RAM.
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pico.mmap.add_region("main",
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BasicRegion(origin=origin, size=size, bus=ram_iface.buses[1]))
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# Allow access from the main CPU to the Block RAM.
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self.add_slave_with_registers(name + "_ram", ram_iface.buses[0],
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SoCRegion(origin=None, size=size, cached=True),
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None)
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def picorv32_add_cl(self, name, param_origin=0x100000):
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""" Add a register area containing the control loop parameters to the
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PicoRV32.
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:param param_origin: The origin of the parameters in the PicoRV32's
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address space. """
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pico = self.get_module(name)
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params = pico.add_cl_params(param_origin, name + "_cl.json")
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self.add_slave_with_registers(name + "_cl", params.mainbus,
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SoCRegion(origin=None, size=params.width, cached=False),
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params.public_registers)
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def add_AD5791(self, name, **kwargs):
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args = SPIMaster.AD5791_PARAMS
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args.update(kwargs)
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spi = SPIMaster(**args)
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self.add_module(name, spi)
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return spi
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def add_LT_adc(self, name, **kwargs):
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args = SPIMaster.LT_ADC_PARAMS
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args.update(kwargs)
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args["mosi"] = Signal()
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# SPI Master brings ss_L low when converting and keeps it high
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# when idle. The ADC is the opposite, so invert the signal here.
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conv_high = Signal()
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self.comb += conv_high.eq(~kwargs["ss_L"])
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spi = SPIMaster(**args)
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self.add_module(name, spi)
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return spi
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def __init__(self,
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variant="a7-100",
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local_ip="192.168.2.50",
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remote_ip="192.168.2.100",
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tftp_port=6969):
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"""
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:param variant: Arty A7 variant. Accepts "a7-35" or "a7-100".
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:param local_ip: The IP that the BIOS will use when transmitting.
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:param remote_ip: The IP that the BIOS will use when retreving
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the Linux kernel via TFTP.
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:param tftp_port: Port that the BIOS uses for TFTP.
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"""
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sys_clk_freq = int(100e6)
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platform = board_spec.Platform(variant=variant, toolchain="f4pga")
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rst = platform.request("cpu_reset")
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self.submodules.crg = _CRG(platform, sys_clk_freq, True, rst)
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# The SoC won't know the origins until LiteX sorts out all the
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# memory regions, so they go into a dictionary directly instead
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# of through MemoryMap.
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self.soc_subregions = {}
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"""
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These source files need to be sorted so that modules
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that rely on another module come later. For instance,
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`control_loop` depends on `control_loop_math`, so
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control_loop_math.v comes before control_loop.v
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If you want to add a new verilog file to the design, look at the
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modules that it refers to and place it the files with those modules.
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Since Yosys doesn't support modern Verilog, only put preprocessed
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(if applicable) files here.
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"""
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platform.add_source("rtl/picorv32/picorv32.v")
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platform.add_source("rtl/spi/spi_master_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_ss.v")
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# SoCCore does not have sane defaults (no integrated rom)
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SoCCore.__init__(self,
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clk_freq=sys_clk_freq,
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toolchain="symbiflow",
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platform = platform,
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bus_standard = "wishbone",
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ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr - Upsilon",
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bus_data_width = 32,
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bus_address_width = 32,
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bus_timeout = int(1e6),
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cpu_type = "vexriscv_smp",
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cpu_count = 1,
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cpu_variant="linux",
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integrated_rom_size=0x20000,
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integrated_sram_size = 0x2000,
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csr_data_width=32,
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csr_address_width=14,
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csr_paging=0x800,
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csr_ordering="big",
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timer_uptime = True)
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# This initializes the connection to the physical DRAM interface.
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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# Synchronous dynamic ram. This is what controls all access to RAM.
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# This houses the "crossbar", which negotiates all RAM accesses to different
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# modules, including the verilog interfaces (waveforms etc.)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 8192
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)
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# Initialize Ethernet
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, dynamic_ip=True)
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# Initialize network information
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self.add_ip(local_ip, "LOCALIP")
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self.add_ip(remote_ip, "REMOTEIP")
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self.add_constant("TFTP_SERVER_PORT", tftp_port)
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# Add pins
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platform.add_extension(io)
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# Add control loop DACs and ADCs.
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self.add_picorv32("pico0")
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self.picorv32_add_cl("pico0")
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# XXX: I don't have the time to restructure my code to make it
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# elegant, that comes when things work
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# If DACs don't work, comment out from here
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module_reset = platform.request("module_reset")
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self.add_AD5791("dac0",
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rst=module_reset,
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miso=platform.request("dac_miso_0"),
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mosi=platform.request("dac_mosi_0"),
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sck=platform.request("dac_sck_0"),
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ss_L=platform.request("dac_ss_L_0"),
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)
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self.add_preemptive_interface("dac0_PI", 2, self.dac0)
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self.add_slave_with_registers("dac0", self.dac0_PI.buses[0],
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SoCRegion(origin=None, size=self.dac0.width, cached=False),
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self.dac0.public_registers)
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self.pico0.mmap.add_region("dac0",
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BasicRegion(origin=0x200000, size=self.dac0.width,
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bus=self.dac0_PI.buses[1],
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registers=self.dac0.public_registers))
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self.add_LT_adc("adc0",
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rst=module_reset,
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miso=platform.request("adc_sdo_0"),
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sck=platform.request("adc_sck_0"),
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ss_L=platform.request("adc_conv_0"),
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spi_wid=18,
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)
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self.add_preemptive_interface("adc0_PI", 2, self.adc0)
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self.add_slave_with_registers("adc0", self.adc0_PI.buses[0],
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SoCRegion(origin=None, size=self.adc0.width, cached=False),
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self.adc0.public_registers)
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self.pico0.mmap.add_region("adc0",
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BasicRegion(origin=0x300000, size=self.adc0.width,
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bus=self.adc0_PI.buses[1],
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registers=self.adc0.public_registers))
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# To here
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def do_finalize(self):
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with open('soc_subregions.json', 'wt') as f:
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json.dump(self.soc_subregions, f)
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def generate_main_cpu_include(csr_file):
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""" Generate Micropython include from a JSON file. """
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with open('mmio.py', 'wt') as out:
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print("from micropython import const", file=out)
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with open(csr_file, 'rt') as f:
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csrs = json.load(f)
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for key in csrs["csr_registers"]:
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if key.startswith("pico0"):
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print(f'{key} = const({csrs["csr_registers"][key]["addr"]})', file=out)
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with open('soc_subregions.json', 'rt') as f:
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subregions = json.load(f)
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for key in subregions:
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if subregions[key] is None:
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print(f'{key} = const({csrs["memories"][key]["base"]})', file=out)
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else:
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print(f'{key}_base = const({csrs["memories"][key]["base"]})', file=out)
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print(f'{key} = {subregions[key].__repr__()}', file=out)
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def main():
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from config import config
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soc =UpsilonSoC(**config)
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builder = Builder(soc, csr_json="csr.json", compile_software=True)
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builder.build()
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generate_main_cpu_include("csr.json")
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if __name__ == "__main__":
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main()
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