367 lines
14 KiB
Python
367 lines
14 KiB
Python
# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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# XXX: PicoRV32 code only handles word-sized registers correctly. Memory
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# regions made up of multiple words are not supported right now.
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from migen import *
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from litex.soc.interconnect.csr import CSRStorage, CSRStatus
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from litex.soc.interconnect.wishbone import Interface, SRAM, Decoder
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from litex.gen import LiteXModule
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from region import *
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class PreemptiveInterface(LiteXModule):
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""" A preemptive interface is a manually controlled Wishbone interface
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that stands between multiple masters (potentially interconnects) and a
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single slave. A master controls which master (or interconnect) has access
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to the slave. This is to avoid bus contention by having multiple buses.
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To use this module, instantiate it. Then connect the controlling master
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to ``self.buses[0]``. Connect the other masters to ``self.buses[1]``, etc.
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Since the buses are seperate, origins don't have to be the same, but the
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size of the region will be the same as the slave interface.
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"""
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def __init__(self, masters_len, slave, addressing="word"):
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"""
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:param masters_len: The amount of buses accessing this slave. This number
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must be greater than one.
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:param slave: The slave device. This object must have an Interface object
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accessable as ``bus``.
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:param addressing: Addressing style of the slave. Default is "word". Note
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that masters may have to convert when selecting self.buses.
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"""
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assert masters_len > 1
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self.buses = []
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self.master_select = CSRStorage(masters_len, name='master_select', description='RW bitstring of which master interconnect to connect to')
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self.slave = slave
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for i in range(masters_len):
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# Add the slave interface each master interconnect sees.
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self.buses.append(Interface(data_width=32, address_width=32, addressing=addressing))
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"""
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Construct a combinatorial case statement. In verilog, the case
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statment would look like
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always @ (*) case (master_select)
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1: begin
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// Assign slave to master 1,
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// Assign all other masters to dummy ports
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end
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2: begin
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// Assign slave to master 2,
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// Assign all other masters to dummy ports
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end
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// more cases:
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default: begin
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// assign slave to master 0
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// Assign all other masters to dummy ports
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end
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Case statement is a dictionary, where each key is either the
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number to match or "default", which is the default case.
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Avoiding latches:
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Left hand sign (assignment) is always an input.
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"""
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def assign_for_case(current_case):
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asn = [ ]
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for j in range(masters_len):
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if current_case == j:
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""" Assign all inputs (for example, slave reads addr
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from master) to outputs. """
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asn += [
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self.slave.bus.adr.eq(self.buses[j].adr),
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self.slave.bus.dat_w.eq(self.buses[j].dat_w),
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self.slave.bus.cyc.eq(self.buses[j].cyc),
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self.slave.bus.stb.eq(self.buses[j].stb),
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self.slave.bus.we.eq(self.buses[j].we),
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self.slave.bus.sel.eq(self.buses[j].sel),
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self.buses[j].dat_r.eq(self.slave.bus.dat_r),
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self.buses[j].ack.eq(self.slave.bus.ack),
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]
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else:
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""" Master bus will always read 0 when they are not
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selected, and writes are ignored. They will still
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get a response to avoid timeouts. """
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asn += [
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self.buses[j].dat_r.eq(0),
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self.buses[j].ack.eq(self.buses[j].cyc & self.buses[j].stb),
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]
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return asn
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cases = {"default": assign_for_case(0)}
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for i in range(1, masters_len):
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cases[i] = assign_for_case(i)
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self.comb += Case(self.master_select.storage, cases)
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class SpecialRegister:
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""" Special registers used for small bits of communiciation. """
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def __init__(self, name, direction, width):
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"""
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:param name: Name of the register, seen in mmio.py.
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:param direction: One of "PR" (pico-read main-write) or "PW" (pico-write main-read).
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:param width: Width in bits, from 0 exclusive to 32 inclusive.
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"""
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assert direction in ["PR", "PW"]
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assert 0 < width and width <= 32
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self.name = name
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self.direction = direction
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self.width = width
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def from_tuples(*tuples):
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return [SpecialRegister(*args) for args in tuples]
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class RegisterInterface(LiteXModule):
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""" Defines "registers" that are either exclusively CPU-write Pico-read
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or CPU-read pico-write. These registers are stored as flip-flops. """
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def __init__(self, registers):
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"""
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:param special_registers: List of instances of SpecialRegister.
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"""
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self.picobus = Interface(data_width = 32, address_width = 32, addressing="byte")
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self.mainbus = Interface(data_width = 32, address_width = 32, addressing="byte")
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pico_case = {"default": self.picobus.dat_r.eq(0xFACADE)}
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main_case = {"default": self.picobus.dat_r.eq(0xEDACAF)}
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# Tuple list of (SpecialRegister, offset)
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self.registers = [(reg, num*0x4) for num, reg in enumerate(registers)]
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for reg, off in self.registers:
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# Round up the width of the stored signal to a multiple of 8.
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wid = round_up_to_word(reg.width)
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sig = Signal(wid)
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def make_write_case(target_bus):
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""" Function to handle write selection for ``target_bus``. """
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writes = []
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if wid >= 8:
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writes.append(If(target_bus.sel[0],
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sig[0:8].eq(target_bus.dat_w[0:8])))
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if wid >= 16:
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writes.append(If(target_bus.sel[1],
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sig[8:16].eq(target_bus.dat_w[8:16])))
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if wid >= 32:
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writes.append(If(target_bus.sel[2],
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sig[16:24].eq(target_bus.dat_w[16:24])))
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writes.append(If(target_bus.sel[3],
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sig[24:32].eq(target_bus.dat_w[24:32])))
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return writes
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if reg.direction == "PR":
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pico_case[off] = self.picobus.dat_r.eq(sig)
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main_case[off] = If(self.mainbus.we,
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*make_write_case(self.mainbus)).Else(
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self.mainbus.dat_r.eq(sig))
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else:
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main_case[off] = self.mainbus.dat_r.eq(sig)
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pico_case[off] = If(self.picobus.we,
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*make_write_case(self.picobus)).Else(
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self.picobus.dat_r.eq(sig))
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self.width = round_up_to_pow_2(sum([off for _, off in self.registers]))
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# Since array indices are exclusive in python (unlike in Verilog),
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# use the bit length of the power of 2, not the bit length of the
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# maximum addressable value.
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bitlen = self.width.bit_length()
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def bus_logic(bus, cases):
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self.sync += If(bus.cyc & bus.stb & ~bus.ack,
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Case(bus.adr[0:bitlen], cases),
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bus.ack.eq(1)
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).Elif(~bus.cyc,
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bus.ack.eq(0))
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bus_logic(self.mainbus, main_case)
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bus_logic(self.picobus, pico_case)
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# Generate addresses
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self.public_registers = {}
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for reg, off in self.registers:
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self.public_registers[reg.name] = {
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"width" : reg.width,
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"direction" : reg.direction,
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"origin": off,
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}
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class RegisterRead(LiteXModule):
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pico_registers = {
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"ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "t1", "t2",
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"s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2",
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"s3", "s4", "s5", "s6", "s7", "t3", "t4", "t5", "t6",
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}
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public_registers = {name: {"origin" : num * 4, "width" : 4, "rw": False} for num, name in enumerate(pico_registers)}
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""" Inspect PicoRV32 registers via Wishbone bus. """
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def __init__(self):
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self.regs = [Signal(32) for i in range(1,32)]
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self.bus = Interface(data_width = 32, address_width = 32, addressing="byte")
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self.width = 0x100
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cases = {"default": self.bus.dat_r.eq(0xdeaddead)}
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for i, reg in enumerate(self.regs):
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cases[i*0x4] = self.bus.dat_r.eq(reg)
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# CYC -> transfer in progress
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# STB -> data is valid on the input lines
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self.sync += [
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
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Case(self.bus.adr[0:7], cases),
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self.bus.ack.eq(1),
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).Elif(self.bus.cyc != 1,
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self.bus.ack.eq(0)
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)
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]
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def gen_pico_header(pico_name):
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""" Generate PicoRV32 C header for this CPU from JSON file. """
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import json
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with open(pico_name + "_mmio.h", "wt") as out:
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print('#pragma once', file=out)
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with open(pico_name + ".json") as f:
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js = json.load(f)
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for region in js:
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if js[region]["registers"] is None:
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continue
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origin = js[region]["origin"]
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for reg in js[region]["registers"]:
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macname = f"{region}_{reg}".upper()
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loc = origin + js[region]["registers"][reg]["origin"]
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print(f"#define {macname} (volatile uint32_t *)({loc})", file=out)
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# Parts of this class come from LiteX.
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#
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# Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018 Sergiusz Bazanski <q3k@q3k.org>
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# Copyright (c) 2019 Antmicro <www.antmicro.com>
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# Copyright (c) 2019 Tim 'mithro' Ansell <me@mith.ro>
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# Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
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# SPDX-License-Identifier: BSD-2-Clause
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class PicoRV32(LiteXModule):
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def add_cl_params(self, origin, dumpname):
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""" Add parameter region for control loop variables. Dumps the
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region information to a JSON file `dumpname`.
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:param origin: Origin of the region for the PicoRV32.
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:param dumpname: File to dump offsets within the region (common to
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both Pico and Main CPU).
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:return: Parameter module (used for accessing metadata).
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"""
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params = RegisterInterface(
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SpecialRegister.from_tuples(
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("cl_I", "PR", 32),
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("cl_P", "PR", 32),
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("deltaT", "PR", 32),
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("setpt", "PR", 32),
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("zset", "PW", 32),
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("zpos", "PW", 32),
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))
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self.add_module("cl_params", params)
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self.mmap.add_region("cl_params", BasicRegion(origin, params.width, params.picobus, params.public_registers))
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return params
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def __init__(self, name, start_addr=0x10000, irq_addr=0x10010, stackaddr=0x100FF):
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self.name = name
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self.masterbus = Interface(data_width=32, address_width=32, addressing="byte")
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self.mmap = MemoryMap(self.masterbus)
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self.resetpin = CSRStorage(1, name="enable", description="PicoRV32 enable")
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self.trap = CSRStatus(8, name="trap", description="Trap condition")
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self.d_adr = CSRStatus(32)
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self.d_dat_w = CSRStatus(32)
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self.dbg_insn_addr = CSRStatus(32)
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self.dbg_insn_opcode = CSRStatus(32)
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self.debug_reg_read = RegisterRead()
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reg_args = {}
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for i in range(1,32):
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reg_args[f"o_dbg_reg_x{i}"] = self.debug_reg_read.regs[i-1]
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mem_valid = Signal()
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mem_instr = Signal()
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mem_ready = Signal()
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mem_addr = Signal(32)
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mem_wdata = Signal(32)
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mem_wstrb = Signal(4)
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mem_rdata = Signal(32)
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self.comb += [
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self.masterbus.adr.eq(mem_addr),
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self.masterbus.dat_w.eq(mem_wdata),
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self.masterbus.we.eq(mem_wstrb != 0),
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self.masterbus.sel.eq(mem_wstrb),
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self.masterbus.cyc.eq(mem_valid),
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self.masterbus.stb.eq(mem_valid),
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self.masterbus.cti.eq(0),
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self.masterbus.bte.eq(0),
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mem_ready.eq(self.masterbus.ack),
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mem_rdata.eq(self.masterbus.dat_r),
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]
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self.comb += [
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self.d_adr.status.eq(mem_addr),
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self.d_dat_w.status.eq(mem_wdata),
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]
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self.specials += Instance("picorv32",
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p_COMPRESSED_ISA = 1,
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p_ENABLE_MUL = 1,
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p_REGS_INIT_ZERO = 1,
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p_PROGADDR_RESET=start_addr,
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p_PROGADDR_IRQ =irq_addr,
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p_STACKADDR = stackaddr,
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o_trap = self.trap.status,
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o_mem_valid = mem_valid,
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o_mem_instr = mem_instr,
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i_mem_ready = mem_ready,
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o_mem_addr = mem_addr,
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o_mem_wdata = mem_wdata,
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o_mem_wstrb = mem_wstrb,
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i_mem_rdata = mem_rdata,
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i_clk = ClockSignal(),
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i_resetn = self.resetpin.storage,
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o_mem_la_read = Signal(),
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o_mem_la_write = Signal(),
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o_mem_la_addr = Signal(32),
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o_mem_la_wdata = Signal(32),
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o_mem_la_wstrb = Signal(4),
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o_pcpi_valid = Signal(),
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o_pcpi_insn = Signal(32),
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o_pcpi_rs1 = Signal(32),
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o_pcpi_rs2 = Signal(32),
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i_pcpi_wr = 0,
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i_pcpi_wait = 0,
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i_pcpi_rd = 0,
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i_pcpi_ready = 0,
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i_irq = 0,
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o_eoi = Signal(32),
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o_trace_valid = Signal(),
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o_trace_data = Signal(36),
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o_dbg_insn_addr = self.dbg_insn_addr.status,
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o_dbg_insn_opcode = self.dbg_insn_opcode.status,
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**reg_args
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)
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def do_finalize(self):
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self.mmap.dump_mmap(self.name + ".json")
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gen_pico_header(self.name)
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self.mmap.finalize()
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