260 lines
10 KiB
Python
260 lines
10 KiB
Python
# Portions of this file incorporate code licensed under the
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# BSD 2-Clause License. See COPYING.
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# There is nothing fundamental about the Arty A7(35|100)T to this
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# design, but another eval board will require some porting.
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from migen import *
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import litex_boards.platforms.digilent_arty as board_spec
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.integration.builder import Builder
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from litex.build.generic_platform import IOStandard, Pins, Subsignal
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from liteeth.phy.mii import LiteEthPHYMII
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# Refer to `A7-constraints.xdc` for pin names.
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# IO with Subsignals make Record types, which have the name of the
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# subsignal as an attribute.
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io = [
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("dac", 0,
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Subsignal("ss", Pins("G13")),
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Subsignal("mosi", Pins("B11")),
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Subsignal("miso", Pins("A11")),
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Subsignal("sck", Pins("D12")),
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IOStandard("LVCMOS33")),
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("dac", 1,
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Subsignal("ss", Pins("D13")),
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Subsignal("mosi", Pins("B18")),
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Subsignal("miso", Pins("A18")),
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Subsignal("sck", Pins("K16")),
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IOStandard("LVCMOS33")),
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("dac", 2,
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Subsignal("ss", Pins("E15")),
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Subsignal("mosi", Pins("E16")),
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Subsignal("miso", Pins("D15")),
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Subsignal("sck", Pins("C15")),
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IOStandard("LVCMOS33")),
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("dac", 3,
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Subsignal("ss", Pins("J17")),
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Subsignal("mosi", Pins("J18")),
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Subsignal("miso", Pins("K15")),
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Subsignal("sck", Pins("J15")),
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IOStandard("LVCMOS33")),
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("dac", 4,
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Subsignal("ss", Pins("U12")),
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Subsignal("mosi", Pins("V12")),
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Subsignal("miso", Pins("V10")),
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Subsignal("sck", Pins("V11")),
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IOStandard("LVCMOS33")),
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("dac", 5,
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Subsignal("ss", Pins("U14")),
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Subsignal("mosi", Pins("V14")),
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Subsignal("miso", Pins("T13")),
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Subsignal("sck", Pins("U13")),
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IOStandard("LVCMOS33")),
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("dac", 6,
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Subsignal("ss", Pins("D4")),
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Subsignal("mosi", Pins("D3")),
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Subsignal("miso", Pins("F4")),
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Subsignal("sck", Pins("F3")),
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IOStandard("LVCMOS33")),
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("dac", 7,
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Subsignal("ss", Pins("E2")),
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Subsignal("mosi", Pins("D2")),
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Subsignal("miso", Pins("H2")),
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Subsignal("sck", Pins("G2")),
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IOStandard("LVCMOS33")),
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("adc", 0,
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Subsignal("conv", Pins("V15")),
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Subsignal("sck", Pins("U16")),
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Subsignal("sdo", Pins("P14")),
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IOStandard("LVCMOS33")),
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("adc", 1,
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Subsignal("conv", Pins("T11")),
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Subsignal("sck", Pins("R12")),
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Subsignal("sdo", Pins("T14")),
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IOStandard("LVCMOS33")),
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("adc", 2,
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Subsignal("conv", Pins("N15")),
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Subsignal("sck", Pins("M16")),
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Subsignal("sdo", Pins("V17")),
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IOStandard("LVCMOS33")),
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("adc", 3,
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Subsignal("conv", Pins("U18")),
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Subsignal("sck", Pins("R17")),
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Subsignal("sdo", Pins("P17")),
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IOStandard("LVCMOS33")),
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("adc", 4,
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Subsignal("conv", Pins("U11")),
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Subsignal("sck", Pins("V16")),
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Subsignal("sdo", Pins("M13")),
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IOStandard("LVCMOS33")),
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("adc", 5,
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Subsignal("conv", Pins("R10")),
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Subsignal("sck", Pins("R11")),
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Subsignal("sdo", Pins("R13")),
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IOStandard("LVCMOS33")),
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("adc", 6,
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Subsignal("conv", Pins("R16")),
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Subsignal("sck", Pins("N16")),
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Subsignal("sdo", Pins("N14")),
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IOStandard("LVCMOS33")),
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("adc", 7,
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Subsignal("conv", Pins("U17")),
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Subsignal("sck", Pins("T18")),
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Subsignal("sdo", Pins("R18")),
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IOStandard("LVCMOS33"))
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]
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class SPIMaster(Module, AutoCSR):
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def __init__(self, wid, clk, pins):
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self.pins = pins
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self.from_slave = CSRStatus(wid, description="Data from slave (Status)")
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self.to_slave = CSRStorage(wid, description="Data to slave (Control)")
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self.finished = CSRStatus(1, description="Finished transmission (Status)")
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self.arm = CSRStorage(1, description="Initiate transmission (Status)")
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self.ss = CSRStorage(1, description="Slave Select (active high)")
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self.comb += self.pins.ss.eq(~self.ss.storage)
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import math
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self.specials += Instance("spi_master",
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p_WID=wid,
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p_WID_LEN=math.ceil(math.log2(wid)),
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p_CYCLE_HALF_WAIT = 3, # 3 + 2 = 5, total sck = 10 cycles
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p_TIMER_LEN = 3,
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p_POLARITY = 0,
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p_PHASE = 1,
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i_clk = clk,
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o_from_slave = self.from_slave.status,
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i_miso = self.pins.miso,
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i_to_slave = self.to_slave.storage,
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o_mosi = self.pins.mosi,
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o_sck_wire = self.pins.sck,
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o_finished = self.finished.status,
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i_arm = self.arm.storage
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)
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class SPIMasterReadOnly(Module, AutoCSR):
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def __init__(self, wid, clk, pins):
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self.pins = pins
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self.from_slave = CSRStatus(wid, description="Data from slave (Status)description=")
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self.finished = CSRStatus(1, description="Finished transmission (Status)description=")
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self.arm = CSRStorage(1, description="Initiate transmission (Status)description=")
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self.conv = CSRStorage(1, description="Conversion (active high)description=")
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self.comb += self.pins.conv.eq(self.conv.storage)
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import math
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self.specials += Instance("spi_master_no_write",
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p_WID=wid,
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p_WID_LEN=math.ceil(math.log2(wid)),
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p_CYCLE_HALF_WAIT = 1, # 1 + 2 = 3, total sck = 6 cycles
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p_TIMER_LEN = 3,
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p_POLARITY = 1,
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p_PHASE = 0,
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i_clk = clk,
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o_from_slave = self.from_slave.status,
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i_miso = self.pins.sdo,
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o_sck_wire = self.pins.sck,
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o_finished = self.finished.status,
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i_arm = self.arm.storage
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)
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# Clock and Reset Generator
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class CryoSNOM1SoC(SoCCore):
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def __init__(self, variant):
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sys_clk_freq = int(100e6)
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platform = board_spec.Platform(variant=variant, toolchain="symbiflow")
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self.submodules.crg = _CRG(platform, sys_clk_freq, True)
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platform.add_source("rtl/spi/spi_master.v")
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platform.add_source("rtl/spi/spi_master_no_write.v")
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# SoCCore does not have sane defaults (no integrated rom)
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SoCCore.__init__(self,
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clk_freq=sys_clk_freq,
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toolchain="symbiflow",
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platform = platform,
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bus_standard = "wishbone",
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ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr CryoSNOM1 0.1",
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bus_data_width = 32,
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bus_address_width = 32,
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bus_timeout = int(1e6),
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cpu_type = "vexriscv",
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integrated_rom_size=0x20000,
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integrated_sram_size = 0x2000,
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csr_data_width=32,
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csr_address_width=14,
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csr_paging=0x800,
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csr_ordering="big",
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timer_uptime = True)
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 8192
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)
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, dynamic_ip=True)
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# Add the DAC and ADC pins as GPIO. They will be used directly
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# by Zephyr.
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platform.add_extension(io)
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for i in range(0,8):
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setattr(self.submodules, f"dac{i}", SPIMaster(24, ClockSignal(), platform.request("dac", i)))
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setattr(self.submodules, f"adc{i}", SPIMasterReadOnly(24, ClockSignal(), platform.request("adc", i)))
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def main():
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soc = CryoSNOM1SoC("a7-35")
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builder = Builder(soc, csr_json="csr.json")
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builder.build()
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if __name__ == "__main__":
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main()
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