Lab_NHMFL
/
upsilon
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Free and open source SoC for Scanning Probe Microscopy
220 Commits 2 Branches 0 Tags 895 KiB
Verilog 44.7%
Python 23.4%
C++ 11.8%
Tcl 7.6%
M4 5.7%
Other 6.8%
Go to file
Peter McGoron 2eba3e1f2a overlay stuff 2023-06-07 21:26:07 -04:00
boot sucessfully boot MAINLINE Linux! 2023-06-05 16:50:08 -04:00
buildroot overlay stuff 2023-06-07 21:26:07 -04:00
copying licensing 2023-05-29 13:56:11 -04:00
creole@52279a9afc creole commits 2023-05-11 11:47:23 -04:00
doc sucessfully boot MAINLINE Linux! 2023-06-05 16:50:08 -04:00
firmware sucessfully boot MAINLINE Linux! 2023-06-05 16:50:08 -04:00
linux overlay stuff 2023-06-07 21:26:07 -04:00
opensbi/litex/vexriscv sucessfully boot MAINLINE Linux! 2023-06-05 16:50:08 -04:00
software proper CSR location generation 2023-05-16 15:02:05 -04:00
.gitignore sucessfully boot MAINLINE Linux! 2023-06-05 16:50:08 -04:00
.gitmodules Revert "roll back to creole master" 2023-04-02 01:56:30 +00:00
GUIDELINES.md GUIDELINES.md 2023-04-21 14:26:37 -04:00
README.md add SPI link 2022-09-17 00:37:42 -04:00

README.md

upsilon

Upsilon is a 100% free and open source STM/AFM controller for FPGAs.

Organization

The project is split into hardware (firmware), kernel (software), and client software (client).

Hardware uses Verilog, LiteX and F4PGA to implement the Soft CPU (Risc-V), hardware communication, PI control loop, image scanning, and tip autoapproach.

Kernel implements the network communication between the hardware and the client software.

The client software receives and interprets data from the hardware.

License

GNU GPL v3.0 or later. Other portions are dual licensed under the CERN OHL-v2-S, or permissive licenses: please view all COPYING files for more legal information.

See also