46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
/* Saturate integers. v0.1
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* Written by Peter McGoron, 2022.
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*/
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module intsat
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#(
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parameter IN_LEN = 64,
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parameter LTRUNC = 32
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)
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(
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input signed [IN_LEN-1:0] inp,
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output signed [IN_LEN-LTRUNC-1:0] outp
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);
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/* Truncating a twos-complement integer can cause overflow.
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* To check for overflow, look at all truncated bits and
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* the most significant bit that will be kept.
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* If they are all 0 or all 1, then there is no truncation.
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*/
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localparam INP_TRUNC_START = IN_LEN - LTRUNC;
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localparam INP_CHECK_START = INP_TRUNC_START - 1;
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localparam OUT_LEN = IN_LEN - LTRUNC;
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/*
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* [ IN_LEN ]
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* [ LTRUNC | OUT_LEN ]
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* * &
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* *: INP_TRUNC_START
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* &: INP_CHECK_START
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*/
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always @ (*) begin
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if (inp[IN_LEN-1:INP_CHECK_START] == {(LTRUNC + 1){inp[IN_LEN-1]}}) begin
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outp[OUT_LEN-1:0] = inp[OUT_LEN-1:0];
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end else if (inp[IN_LEN-1]) begin
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// most negative number: 1000000....
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outp[OUT_LEN-1:0] = {1'b1,{(OUT_LEN-1){1'b0}}};
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end else begin
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// most positive number: 0111111....
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outp[OUT_LEN-1:0] = {1'b0,{(OUT_LEN-1){1'b1}}};
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end
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end
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endmodule
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