251 lines
10 KiB
Python
251 lines
10 KiB
Python
# This file incorporates code from litex-boards.
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# BSD 2-Clause License
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#
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# Copyright (c) Copyright 2012-2022 Enjoy-Digital.
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# Copyright (c) Copyright 2012-2022 / LiteX-Hub community.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# There is nothing fundamental about the Arty A7(35|100)T to this
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# design, but another eval board will require some porting.
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from migen import *
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import litex_boards.platforms.digilent_arty as board_spec
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.integration.builder import Builder
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from litex.build.generic_platform import IOStandard, Pins, Subsignal
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from liteeth.phy.mii import LiteEthPHYMII
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# Refer to `A7-constraints.xdc` for pin names.
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# IO with Subsignals make Record types, which have the name of the
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# subsignal as an attribute.
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io = [
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("dac", 0,
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Subsignal("ss", Pins("G13")),
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Subsignal("mosi", Pins("B11")),
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Subsignal("miso", Pins("A11")),
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Subsignal("sck", Pins("D12")),
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IOStandard("LVCMOS33")),
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("dac", 1,
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Subsignal("ss", Pins("D13")),
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Subsignal("mosi", Pins("B18")),
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Subsignal("miso", Pins("A18")),
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Subsignal("sck", Pins("K16")),
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IOStandard("LVCMOS33")),
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("dac", 2,
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Subsignal("ss", Pins("E15")),
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Subsignal("mosi", Pins("E16")),
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Subsignal("miso", Pins("D15")),
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Subsignal("sck", Pins("C15")),
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IOStandard("LVCMOS33")),
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("dac", 3,
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Subsignal("ss", Pins("J17")),
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Subsignal("mosi", Pins("J18")),
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Subsignal("miso", Pins("K15")),
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Subsignal("sck", Pins("J15")),
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IOStandard("LVCMOS33")),
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("dac", 4,
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Subsignal("ss", Pins("U12")),
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Subsignal("mosi", Pins("V12")),
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Subsignal("miso", Pins("V10")),
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Subsignal("sck", Pins("V11")),
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IOStandard("LVCMOS33")),
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("dac", 5,
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Subsignal("ss", Pins("U14")),
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Subsignal("mosi", Pins("V14")),
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Subsignal("miso", Pins("T13")),
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Subsignal("sck", Pins("U13")),
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IOStandard("LVCMOS33")),
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("dac", 6,
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Subsignal("ss", Pins("D4")),
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Subsignal("mosi", Pins("D3")),
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Subsignal("miso", Pins("F4")),
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Subsignal("sck", Pins("F3")),
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IOStandard("LVCMOS33")),
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("dac", 7,
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Subsignal("ss", Pins("E2")),
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Subsignal("mosi", Pins("D2")),
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Subsignal("miso", Pins("H2")),
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Subsignal("sck", Pins("G2")),
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IOStandard("LVCMOS33")),
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("adc", 0,
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Subsignal("conv", Pins("V15")),
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Subsignal("sck", Pins("U16")),
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Subsignal("sdo", Pins("P14")),
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IOStandard("LVCMOS33")),
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("adc", 1,
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Subsignal("conv", Pins("T11")),
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Subsignal("sck", Pins("R12")),
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Subsignal("sdo", Pins("T14")),
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IOStandard("LVCMOS33")),
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("adc", 2,
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Subsignal("conv", Pins("N15")),
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Subsignal("sck", Pins("M16")),
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Subsignal("sdo", Pins("V17")),
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IOStandard("LVCMOS33")),
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("adc", 3,
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Subsignal("conv", Pins("U18")),
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Subsignal("sck", Pins("R17")),
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Subsignal("sdo", Pins("P17")),
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IOStandard("LVCMOS33")),
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("adc", 4,
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Subsignal("conv", Pins("U11")),
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Subsignal("sck", Pins("V16")),
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Subsignal("sdo", Pins("M13")),
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IOStandard("LVCMOS33")),
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("adc", 5,
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Subsignal("conv", Pins("R10")),
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Subsignal("sck", Pins("R11")),
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Subsignal("sdo", Pins("R13")),
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IOStandard("LVCMOS33")),
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("adc", 6,
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Subsignal("conv", Pins("R16")),
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Subsignal("sck", Pins("N16")),
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Subsignal("sdo", Pins("N14")),
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IOStandard("LVCMOS33")),
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("adc", 7,
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Subsignal("conv", Pins("U17")),
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Subsignal("sck", Pins("T18")),
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Subsignal("sdo", Pins("R18")),
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IOStandard("LVCMOS33"))
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]
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class DACThroughGPIO(Module, AutoCSR):
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def __init__(self, pins):
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self._miso = CSRStatus(1, description="Master In, Slave Out (Status)")
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# Read as [MSB ... LSB]
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self._ctrl = CSRStorage(3, description="SS, SCK, MOSI (Control)")
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self._pins = pins
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self.comb += self._miso.status.eq(self._pins.miso)
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self.comb += self._pins.ss.eq(~self._ctrl.storage[2])
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self.comb += self._pins.mosi.eq(self._ctrl.storage[1])
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self.comb += self._pins.sck.eq(self._ctrl.storage[0])
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class ADCThroughGPIO(Module, AutoCSR):
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def __init__(self, pins):
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self._pins = pins
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self._conv = CSRStorage(1, description="Conversion Signal (Control)")
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self._sck = CSRStorage(1, description="Serial Clock (Control)")
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self._sdo = CSRStatus(1, description="Serial Data Output (Status)")
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self.comb += self._pins.conv.eq(self._conv.storage)
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self.comb += self._pins.sck.eq(self._sck.storage)
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self.comb += self._sdo.status.eq(self._pins.sdo)
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class CryoSNOM1SoC(SoCCore):
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def __init__(self, variant):
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sys_clk_freq = int(100e6)
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platform = board_spec.Platform(variant=variant, toolchain="symbiflow")
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self.submodules.crg = _CRG(platform, sys_clk_freq, True)
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# SoCCore does not have sane defaults (no integrated rom)
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SoCCore.__init__(self,
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clk_freq=sys_clk_freq,
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toolchain="symbiflow",
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platform = platform,
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bus_standard = "wishbone",
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ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr CryoSNOM1 0.1",
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bus_data_width = 32,
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bus_address_width = 32,
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bus_timeout = int(1e6),
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cpu_type = "vexriscv",
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integrated_rom_size=0x20000,
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integrated_sram_size = 0x2000,
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csr_data_width=32,
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csr_address_width=14,
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csr_paging=0x800,
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csr_ordering="big",
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timer_uptime = True)
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 8192
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)
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, dynamic_ip=True)
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# Add the DAC and ADC pins as GPIO. They will be used directly
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# by Zephyr.
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platform.add_extension(io)
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for i in range(0,8):
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setattr(self.submodules, f"dac{i}", DACThroughGPIO(platform.request("dac", i)))
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setattr(self.submodules, f"adc{i}", ADCThroughGPIO(platform.request("adc", i)))
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def main():
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soc = CryoSNOM1SoC("a7-35")
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builder = Builder(soc, csr_json="csr.json")
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builder.build()
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if __name__ == "__main__":
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main()
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