244 lines
10 KiB
Python
244 lines
10 KiB
Python
# Portions of this file incorporate code licensed under the
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# BSD 2-Clause License. See COPYING.
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# There is nothing fundamental about the Arty A7(35|100)T to this
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# design, but another eval board will require some porting.
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from migen import *
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import litex_boards.platforms.digilent_arty as board_spec
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.integration.builder import Builder
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from litex.build.generic_platform import IOStandard, Pins, Subsignal
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from litedram.frontend.dma import LiteDRAMDMAReader
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from liteeth.phy.mii import LiteEthPHYMII
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# Refer to `A7-constraints.xdc` for pin names.
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io = [
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("dac_ss_L", 0, Pins("G13 D13 E15 J17 U12 U14 D4 E2"), IOStandard("LVCMOS33")),
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("dac_mosi", 0, Pins("B11 B18 E16 J18 V12 V14 D3 D2"), IOStandard("LVCMOS33")),
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("dac_miso", 0, Pins("A11 A18 D15 K15 V10 T13 F4 H2"), IOStandard("LVCMOS33")),
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("dac_sck", 0, Pins("D12 K16 C15 J15 V11 U13 F3 G2"), IOStandard("LVCMOS33")),
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("adc_conv", 0, Pins("V15 T11 N15 U18 U11 R10 R16 U17"), IOStandard("LVCMOS33")),
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("adc_sck", 0, Pins("U16 R12 M16 R17 V16 R11 N16 T18"), IOStandard("LVCMOS33")),
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("adc_sdo", 0, Pins("P14 T14 V17 P17 M13 R13 N14 R18"), IOStandard("LVCMOS33"))
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]
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# TODO: Generate widths based off of include files (m4 generated)
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class Base(Module, AutoCSR):
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""" The subclass AutoCSR will automatically make CSRs related
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to this class when those CSRs are attributes (i.e. accessed by
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`self.csr_name`) of instances of this class.
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Since there are a lot of input and output wires, the CSRs are
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assigned using `setattr()`.
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CSRs are for input wires (`CSRStorage`) or output wires
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(`CSRStatus`). The first argument to the CSR constructor is
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the amount of bits the CSR takes. The `name` keyword argument
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is required since the constructor needs the name of the attribute.
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The `description` keyword is used for documentation.
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In LiteX, modules in separate Verilog files are instantiated as
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self.specials += Instance(
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"module_name",
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PARAMETER_NAME=value,
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i_input = input_port,
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o_output = output_port,
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...
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)
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Since the "base" module has a bunch of repeated input and output
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pins that have to be connected to CSRs, the LiteX wrapper uses
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keyword arguments to pass all the arguments.
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"""
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def _make_csr(self, name, csrclass, csrlen, description, num=None):
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""" Add a CSR for a pin `f"{name_{num}"` with CSR type
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`csrclass`. This will automatically handle the `i_` and
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`o_` prefix in the keyword arguments.
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"""
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if name not in self.csrdict.keys():
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self.csrdict[name] = csrlen
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if num is not None:
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name = f"{name}_{num}"
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csr = csrclass(csrlen, name=name, description=description)
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setattr(self, name, csr)
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if csrclass is CSRStorage:
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self.kwargs[f'i_{name}'] = csr.storage
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elif csrclass is CSRStatus:
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self.kwargs[f'o_{name}'] = csr.status
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else:
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raise Exception(f"Unknown class {csrclass}")
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def __init__(self, clk, sdram, platform):
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self.kwargs = {}
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self.csrdict = {}
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for i in range(0,8):
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self._make_csr("dac_sel", CSRStorage, 3, f"Select DAC {i} Output", num=i)
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self._make_csr("dac_finished", CSRStatus, 1, f"DAC {i} Transmission Finished Flag", num=i)
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self._make_csr("dac_arm", CSRStorage, 1, f"DAC {i} Arm Flag", num=i)
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self._make_csr("from_dac", CSRStatus, 24, f"DAC {i} Received Data", num=i)
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self._make_csr("to_dac", CSRStorage, 24, f"DAC {i} Data to Send", num=i)
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self._make_csr("wf_arm", CSRStorage, 1, f"Waveform {i} Arm Flag", num=i)
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self._make_csr("wf_halt_on_finish", CSRStorage, 1, f"Waveform {i} Halt on Finish Flag", num=i)
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self._make_csr("wf_finished", CSRStatus, 1, f"Waveform {i} Finished Flag", num=i)
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self._make_csr("wf_running", CSRStatus, 1, f"Waveform {i} Running Flag", num=i)
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self._make_csr("wf_time_to_wait", CSRStorage, 16, f"Waveform {i} Wait Time", num=i)
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self._make_csr("wf_refresh_start", CSRStorage, 1, f"Waveform {i} Data Refresh Start Flag", num=i)
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self._make_csr("wf_refresh_finished", CSRStatus, 1, f"Waveform {i} Data Refresh Finished Flag", num=i)
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self._make_csr("wf_start_addr", CSRStorage, 32, f"Waveform {i} Data Addr", num=i)
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port = sdram.crossbar.get_port()
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setattr(self, f"wf_sdram_{i}", LiteDRAMDMAReader(port))
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cur_sdram = getattr(self, f"wf_sdram_{i}")
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self.kwargs[f"o_wf_ram_dma_addr_{i}"] = cur_sdram.sink.address
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self.kwargs[f"i_wf_ram_word_{i}"] = cur_sdram.source.data
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self.kwargs[f"o_wf_ram_read_{i}"] = cur_sdram.sink.valid
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self.kwargs[f"i_wf_ram_valid_{i}"] = cur_sdram.source.valid
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self._make_csr("adc_finished", CSRStatus, 1, f"ADC {i} Finished Flag", num=i)
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self._make_csr("adc_arm", CSRStorage, 1, f"ADC {i} Arm Flag", num=i)
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self._make_csr("from_adc", CSRStatus, 32, f"ADC {i} Received Data", num=i)
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self._make_csr("adc_sel_0", CSRStorage, 2, "Select ADC 0 Output")
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self._make_csr("cl_in_loop", CSRStatus, 1, "Control Loop Loop Enabled Flag")
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self._make_csr("cl_cmd", CSRStorage, 8, "Control Loop Command Input")
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self._make_csr("cl_word_in", CSRStorage, 64, "Control Loop Data Input")
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self._make_csr("cl_word_out", CSRStatus, 64, "Control Loop Data Output")
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self._make_csr("cl_start_cmd", CSRStorage, 1, "Control Loop Command Start Flag")
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self._make_csr("cl_finish_cmd", CSRStatus, 1, "Control Loop Command Finished Flag")
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self.kwargs["i_clk"] = clk
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self.kwargs["i_dac_miso"] = platform.request("dac_miso")
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self.kwargs["o_dac_mosi"] = platform.request("dac_mosi")
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self.kwargs["o_dac_sck"] = platform.request("dac_sck")
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self.kwargs["o_dac_ss_L"] = platform.request("dac_ss_L")
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self.kwargs["o_adc_conv"] = platform.request("adc_conv")
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self.kwargs["i_adc_sdo"] = platform.request("adc_sdo")
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self.kwargs["o_adc_sck"] = platform.request("adc_sck")
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with open("csr_bitwidth.json", mode='w') as f:
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import json
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json.dump(self.csrdict, f)
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self.specials += Instance("base", **self.kwargs)
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# Clock and Reset Generator
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# I don't know how this works, I only know that it does.
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# TODO: Connect cpu_reset pin to Verilog modules.
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class CryoSNOM1SoC(SoCCore):
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def __init__(self, variant):
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sys_clk_freq = int(100e6)
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platform = board_spec.Platform(variant=variant, toolchain="f4pga")
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self.submodules.crg = _CRG(platform, sys_clk_freq, True)
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# These source files need to be sorted so that modules
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# that rely on another module come later. For instance,
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# `control_loop` depends on `control_loop_math`, so
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# control_loop_math.v comes before control_loop.v
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platform.add_source("rtl/spi/spi_switch_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_no_write_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_no_read_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_ss_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_ss_no_write_preprocessed.v")
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platform.add_source("rtl/spi/spi_master_ss_no_read_preprocessed.v")
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platform.add_source("rtl/control_loop/sign_extend.v")
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platform.add_source("rtl/control_loop/intsat.v")
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platform.add_source("rtl/control_loop/boothmul.v")
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platform.add_source("rtl/control_loop/control_loop_math.v")
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platform.add_source("rtl/control_loop/control_loop.v")
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platform.add_source("rtl/waveform/bram_interface_preprocessed.v")
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platform.add_source("rtl/waveform/waveform_preprocessed.v")
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platform.add_source("rtl/base/base.v")
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# SoCCore does not have sane defaults (no integrated rom)
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SoCCore.__init__(self,
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clk_freq=sys_clk_freq,
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toolchain="symbiflow",
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platform = platform,
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bus_standard = "wishbone",
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ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr - Upsilon",
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bus_data_width = 32,
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bus_address_width = 32,
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bus_timeout = int(1e6),
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cpu_type = "vexriscv",
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integrated_rom_size=0x20000,
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integrated_sram_size = 0x2000,
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csr_data_width=32,
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csr_address_width=14,
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csr_paging=0x800,
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csr_ordering="big",
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timer_uptime = True)
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# This initializes the connection to the physical DRAM interface.
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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# Synchronous dynamic ram. This is what controls all access to RAM.
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# This houses the "crossbar", which negotiates all RAM accesses to different
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# modules, including the verilog interfaces (waveforms etc.)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 8192
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)
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, dynamic_ip=True)
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# Add the DAC and ADC pins as GPIO. They will be used directly
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# by Zephyr.
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platform.add_extension(io)
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self.submodules.base = Base(ClockSignal(), self.sdram, platform)
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def main():
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soc = CryoSNOM1SoC("a7-100")
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builder = Builder(soc, csr_json="csr.json", compile_software=True)
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builder.build()
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if __name__ == "__main__":
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main()
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