102 lines
2.2 KiB
Verilog
102 lines
2.2 KiB
Verilog
/* Autoapproach module. This module applies a waveform located in memory
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* (and copied into Block RAM). This waveform is arbitrary but of fixed
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* length.
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* time in between sent sample, total period 10-50ms
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*/
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module autoapproach #(
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parameter DAC_WID = 24,
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parameter DAC_DATA_WID = 20,
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parameter ADC_WID = 24,
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parameter TIMER_WID = 32
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) (
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input clk,
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input arm,
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output stopped,
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output detected,
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input polarity,
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input [ADC_WID-1:0] setpoint,
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input [TIMER_WID-1:0] time_to_wait,
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/* BRAM memory interface. Each pulse returns the next value in
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* the sequence, and also informs the module if the sequence
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* is completed. The kernel interacts primarily with this interface.
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*/
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input [DAC_DATA_WID-1:0] word,
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output word_next,
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input word_last,
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input word_ok,
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output word_rst,
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/* DAC wires. */
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input dac_finished,
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output dac_arm,
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input [DAC_WID-1:0] dac_in,
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output [DAC_WID-1:0] dac_out,
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input adc_finished,
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output adc_arm,
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input [ADC_WID-1:0] measurement
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);
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localparam WAIT_ON_ARM = 0;
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localparam DO_WAIT = 1;
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localparam RECV_WORD = 2;
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localparam WAIT_ON_DAC = 3;
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localparam WAIT_ON_DETECTION = 4;
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localparam DETECTED = 5;
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reg [2:0] state = WAIT_ON_ARM;
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reg [TIMER_WID-1:0] wait_timer = 0;
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always @ (posedge clk) case (state)
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WAIT_ON_ARM: if (arm) begin
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state <= DO_WAIT;
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stopped <= 0;
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wait_timer <= time_to_wait;
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end else begin
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stopped <= 1;
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word_rst <= 1;
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end
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DO_WAIT: if (!arm) begin
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state <= WAIT_ON_ARM;
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end else if (wait_timer == 0) begin
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word_next <= 1;
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state <= RECV_WORD;
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wait_timer <= time_to_wait;
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end else begin
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wait_timer <= wait_timer - 1;
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end
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RECV_WORD: if (word_ok) begin
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dac_out <= {4'b0001, word};
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dac_arm <= 1;
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word_next <= 0;
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state <= WAIT_ON_DAC;
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end
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WAIT_ON_DAC: if (dac_finished) begin
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dac_arm <= 0;
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/* Was the last word read *the* last word? */
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if (word_last) begin
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state <= WAIT_ON_DETECTION;
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adc_arm <= 1;
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end else begin
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state <= WAIT_ON_ARM;
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end
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endcase
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WAIT_ON_DETECTION: if (adc_finished) begin
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if ((polarity && measurement >= setpt) ||
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(!polarity && measurement <= setpt)) begin
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state <= DETECTED;
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detected <= 1;
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end
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end
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DETECTED: if (!arm) begin
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state <= WAIT_ON_ARM;
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detected <= 0;
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end
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endcase
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endmodule
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