66 lines
1.7 KiB
Verilog
66 lines
1.7 KiB
Verilog
/* Copyright 2024 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*
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* This BRAM can only handle aligned accesses.
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*/
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module bram #(
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/* Width of the memory bus */
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parameter BUS_WID = 32,
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/* Width of a request. */
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parameter WORD_WID = 32,
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/* Bitmask used to extract the RAM location in the buffer. */
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parameter ADDR_MASK = 32'h1FFF
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) (
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input clk,
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input wb_cyc,
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input wb_stb,
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input wb_we,
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input [4-1:0] wb_sel,
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input [BUS_WID-1:0] wb_addr,
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input [BUS_WID-1:0] wb_dat_w,
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output reg wb_ack,
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output reg [BUS_WID-1:0] wb_dat_r
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);
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initial wb_ack <= 0;
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initial wb_dat_r <= 0;
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/* When the size of the memory is a power of 2, the mask is the
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* last addressable index in the array.
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*
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* Since this buffer stores words, this is divided by 4 (32 bits).
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* When accessing a single byte, the address
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* 0b......Xab
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* is shifted to the right by two bits, throwing away "ab". This indexes
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* the 32 bit word that contains the address. This applies to halfwords
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* and words as long as the accesses are aligned.
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*/
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(* ram_style = "block" *)
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reg [WORD_WID-1:0] buffer [(ADDR_MASK >> 2):0];
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/* Current index into the buffer. */
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wire [13-1:0] ind = (wb_addr & ADDR_MASK) >> 2;
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always @ (posedge clk) if (wb_cyc && wb_stb && !wb_ack) begin
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wb_ack <= 1;
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if (wb_we) begin
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if (wb_sel[0])
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buffer[ind][7:0] <= wb_dat_w[7:0];
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if (wb_sel[1])
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buffer[ind][15:8] <= wb_dat_w[15:8];
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if (wb_sel[2])
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buffer[ind][23:16] <= wb_dat_w[23:16];
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if (wb_sel[3])
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buffer[ind][31:24] <= wb_dat_w[31:24];
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end else begin
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wb_dat_r <= buffer[ind];
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end
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end else if (!wb_stb) begin
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wb_ack <= 0;
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end
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endmodule
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