Shell-ac 556db1f361 Add files via upload ... Verilog signal propagation testbench for the intsat module		2023-01-30 14:09:49 -05:00
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autoapproach	refactoring: move dma simulation to verilog	2023-01-30 13:54:17 +00:00
control_loop	Add files via upload	2023-01-30 14:09:49 -05:00
raster	raster simulate	2022-12-23 20:22:48 +00:00
spi	correctly (and crudely) simulate control loop	2022-11-24 09:48:19 -05:00
testbench.hpp	refactoring: move dma simulation to verilog	2023-01-30 13:54:17 +00:00
util.hpp	more refactoring	2023-01-30 13:07:34 +00:00