69 lines
1.1 KiB
Verilog
69 lines
1.1 KiB
Verilog
module adc_sim #(
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parameter POLARITY = 1,
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parameter PHASE = 0,
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parameter WID = 18,
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parameter WID_LEN = 5
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) (
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input clk,
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input [WID-1:0] indat,
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output reg request,
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input fulfilled,
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output err,
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output miso,
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input sck,
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input ss_L
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);
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wire ss = !ss_L;
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reg ss_raised = 0;
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reg fulfilled_raised = 0;
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reg ss_buf_L = 1;
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reg [WID-1:0] data = 0;
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reg rdy = 0;
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wire spi_fin;
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always @ (posedge clk) begin
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if (ss && !ss_raised) begin
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request <= 1;
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ss_raised <= 1;
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end else if (ss_raised && !ss) begin
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ss_raised <= 0;
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ss_buf_L <= 1;
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rdy <= 0;
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request <= 0;
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fulfilled_raised <= 0;
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end else if (ss_raised && request && fulfilled && !fulfilled_raised) begin
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data <= indat;
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fulfilled_raised <= 1;
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request <= 0;
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rdy <= 1;
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end else if (ss_raised && !fulfilled && fulfilled_raised) begin
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fulfilled_raised <= 0;
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ss_buf_L <= 0;
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end else if (spi_fin) begin
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rdy <= 0;
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end
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end
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spi_slave_no_read #(
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.WID(WID),
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.WID_LEN(WID_LEN),
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.POLARITY(POLARITY),
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.PHASE(PHASE)
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) spi (
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.clk(clk),
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.sck(sck),
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.ss_L(ss_buf_L),
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.miso(miso),
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.to_master(data),
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.finished(spi_fin),
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.rdy(rdy),
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.err(err)
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);
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endmodule
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`undefineall
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