124 lines
2.2 KiB
Verilog
124 lines
2.2 KiB
Verilog
/* (c) Peter McGoron 2022 v0.3
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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/* spi master with integrated ability to wait a certain amount of cycles
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* after activating SS.
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*/
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module `SPI_MASTER_SS_NAME
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#(
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parameter WID = 24,
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parameter WID_LEN = 5,
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parameter CYCLE_HALF_WAIT = 1,
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parameter TIMER_LEN = 3,
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parameter SS_WAIT = 1,
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parameter SS_WAIT_TIMER_LEN = 2,
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parameter POLARITY = 0,
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parameter PHASE = 0
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)
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(
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input clk,
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input rst_L,
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`ifndef SPI_MASTER_NO_READ
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output [WID-1:0] from_slave,
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input miso,
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`endif
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`ifndef SPI_MASTER_NO_WRITE
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input [WID-1:0] to_slave,
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output reg mosi,
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`endif
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output sck_wire,
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output finished,
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output ready_to_arm,
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output ss_L,
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input arm
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);
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reg ss = 0;
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reg arm_master = 0;
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assign ss_L = !ss;
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`SPI_MASTER_NAME #(
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.WID(WID),
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.WID_LEN(WID_LEN),
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.CYCLE_HALF_WAIT(CYCLE_HALF_WAIT),
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.TIMER_LEN(TIMER_LEN),
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.POLARITY(POLARITY),
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.PHASE(PHASE)
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) master (
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.clk(clk),
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.rst_L(rst_L),
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`ifndef SPI_MASTER_NO_READ
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.from_slave(from_slave),
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.miso(miso),
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`endif
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`ifndef SPI_MASTER_NO_WRITE
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.to_slave(to_slave),
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.mosi(mosi),
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`endif
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.sck_wire(sck_wire),
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.finished(finished),
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.ready_to_arm(ready_to_arm),
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.arm(arm_master)
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);
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localparam WAIT_ON_ARM = 0;
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localparam WAIT_ON_SS = 1;
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localparam WAIT_ON_MASTER = 2;
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localparam WAIT_ON_ARM_DEASSERT = 3;
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reg [2:0] state = WAIT_ON_ARM;
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reg [SS_WAIT_TIMER_LEN-1:0] timer = 0;
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task master_arm();
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arm_master <= 1;
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state <= WAIT_ON_MASTER;
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endtask
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always @ (posedge clk) begin
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if (!rst_L) begin
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state <= WAIT_ON_ARM;
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timer <= 0;
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arm_master <= 0;
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ss <= 0;
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end else case (state)
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WAIT_ON_ARM: begin
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if (arm) begin
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timer <= 1;
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if (SS_WAIT == 0) begin
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master_arm();
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end else begin
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timer <= 1;
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state <= WAIT_ON_SS;
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end
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ss <= 1;
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end
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end
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WAIT_ON_SS: begin
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if (timer == SS_WAIT) begin
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master_arm();
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end else begin
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timer <= timer + 1;
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end
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end
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WAIT_ON_MASTER: begin
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if (finished) begin
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state <= WAIT_ON_ARM_DEASSERT;
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ss <= 0;
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end
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end
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WAIT_ON_ARM_DEASSERT: begin
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if (!arm) begin
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state <= WAIT_ON_ARM;
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arm_master <= 0;
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end
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end
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endcase
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end
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endmodule
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`undefineall
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