8 lines
298 B
Makefile
8 lines
298 B
Makefile
# Generate verilog from m4 file
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#m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
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# NOTE: f4pga yosys does not support `line directives. Use above for debug.
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%.v: %.v.m4
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m4 -P $< > $@
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%_preprocessed.v: %.v
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verilator -P -E $< > $@
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