32 lines
1.0 KiB
ReStructuredText
32 lines
1.0 KiB
ReStructuredText
Copyright 2024 (C) Peter McGoron.
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This file is a part of Upsilon, a free and open source software project.
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For license terms, refer to the files in ``doc/copying`` in the Upsilon
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source distribution.
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***************************************************
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This manual describes the hardware portion of Upsilon.
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===============
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LiteX and Migen
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===============
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Migen is a library that generates Verilog using Python. It uses Python
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objects and methods as a DSL within Python.
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LiteX is a SoC generator using Migen. LiteX includes RAM, CPU, bus logic,
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etc. LiteX is very powerful but not well documented.
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================
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System on a Chip
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================
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Upsilon uses a RISC-V CPU running Linux to power most operations. It currently
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uses a single-core VexRISC-V CPU running mainline Linux 5.x. How the main core
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communicates with the hardware is a software issue: see /doc/software.rst .
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Basic configuration of the SoC is done in the /gateware/config.py file. If
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this file does not exist, copy /gateware/config.py.def to /gateware/config.py .
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This is the default config.
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