103 lines
1.7 KiB
Verilog
103 lines
1.7 KiB
Verilog
module top
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#(
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parameter ADC_WID = 18,
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parameter DAC_WID = 24,
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parameter ADC_POLARITY = 1,
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parameter ADC_PHASE = 0,
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parameter DAC_DATA_WID = 20,
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parameter CONSTS_WID = 48,
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parameter DELAY_WID = 16
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)(
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input clk,
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input arm,
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input signed [ADC_WID-1:0] measured_data,
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output signed [DAC_WID-1:0] output_data,
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input signed [ADC_WID-1:0] setpt,
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input signed [CONSTS_WID-1:0] alpha,
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input signed [CONSTS_WID-1:0] cl_p,
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input [DELAY_WID-1:0] dy,
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output signed [ADC_WID:0] err,
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output signed [CONSTS_WID-1:0] adj
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);
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wire adc_sck;
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wire adc_ss;
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wire adc_miso;
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reg adc_finished = 0;
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wire dac_mosi;
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wire dac_sck;
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wire dac_ss;
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reg dac_finished = 0;
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/* Emulate a control loop environment with simulator controlled
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SPI interfaces.
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*/
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/* ADC */
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spi_slave_no_write #(
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.WID(ADC_WID),
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.WID_LEN(5),
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.ADC_POLARITY(ADC_POLARITY),
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.ADC_PHASE(ADC_PHASE)
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)(
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.clk(clk),
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.to_master(measured_data),
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.sck(adc_sck),
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.ss_L(!adc_ss),
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.miso(adc_miso),
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.rdy(!dac_ss),
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.finished(adc_finished)
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);
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/* DAC */
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spi_slave_no_read #(
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.WID(DAC_WID),
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.WID_LEN(5),
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.DAC_POLARITY(DAC_POLARITY),
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.DAC_PHASE(DAC_PHASE)
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)(
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.clk(clk),
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.from_master(output_data),
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.mosi(dac_mosi),
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.sck(dac_sck),
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.ss_L(!dac_ss),
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.rdy(!dac_ss),
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.finished(dac_finished)
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);
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control_loop #(
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.ADC_WID(ADC_WID),
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.DAC_WID(DAC_WID),
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.DAC_DATA_WID(DAC_DATA_WID),
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.CONSTS_WID(CONSTS_WID),
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.DELAY_WID(DELAY_WID),
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.ADC_POLARITY(ADC_POLARITY),
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.ADC_PHASE(ADC_PHASE),
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.DAC_POLARITY(DAC_POLARITY),
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.DAC_PHASE(DAC_PHASE)
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) cloop (
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.clk(clk),
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.arm(arm),
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.adc_sck(adc_sck),
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.adc_in(adc_miso),
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.adc_conv(adc_ss),
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.dac_sck(dac_sck),
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.dac_ss(dac_ss),
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.dac_out(dac_mosi),
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.setpt_in(setpt),
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.cl_alpha_in(alpha),
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.cl_p_in(cl),
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.delay_in(dy),
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.err(err_cur),
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.adj(adj)
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);
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endmodule
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