upsilon/firmware/rtl/control_loop
Peter McGoron 05f8878751 add submodules and switch 2023-03-03 08:06:50 +00:00
..
Makefile control loop simulator passes lint 2022-11-21 21:41:50 -05:00
adc_sim.v fix adc_sim 2022-11-21 22:04:46 -05:00
boothmul.v Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00
boothmul_sim.cpp import updated boothmul 2022-11-11 22:14:50 -05:00
control_loop.v add submodules and switch 2023-03-03 08:06:50 +00:00
control_loop_cmds.vh control loop simulator passes lint 2022-11-21 21:41:50 -05:00
control_loop_math.v reverify math 2022-11-21 22:24:37 -05:00
control_loop_math_implementation.cpp Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00
control_loop_math_implementation.h Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00
control_loop_math_sim.cpp reverify math 2022-11-21 22:24:37 -05:00
control_loop_sim.cpp Added more comments to file 2023-01-29 16:31:15 -05:00
control_loop_sim_top.v control loop simulator passes lint 2022-11-21 21:41:50 -05:00
dac_sim.v fix dac simulation 2022-11-21 22:56:40 -05:00
intro.md integrate control_loop_math into control_loop 2022-11-17 19:07:21 -05:00
intsat.v add everything im working on 2022-09-16 18:01:34 -04:00
intsat_sim.cpp move simulators to the same directory of the simulated core 2022-10-17 00:45:19 -04:00
intsat_testbench.v Add files via upload 2023-01-30 14:09:49 -05:00
sign_extend.v Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00