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Free and open source SoC for Scanning Probe Microscopy
30 Commits 2 Branches 0 Tags 895 KiB
Verilog 44.7%
Python 23.4%
C++ 11.8%
Tcl 7.6%
M4 5.7%
Other 6.8%
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Peter McGoron 7de27a2408 change converter code to drive new verilog 2022-07-27 09:33:11 -04:00
firmware change CSR types 2022-07-27 09:32:49 -04:00
software change converter code to drive new verilog 2022-07-27 09:33:11 -04:00
.gitignore add .gitignore 2022-07-14 15:48:07 -04:00