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base
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proper CSR location generation
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2023-05-16 15:02:05 -04:00 |
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control_loop
|
properly add boothmul
|
2023-05-30 14:46:45 -04:00 |
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raster
|
arty.xdc for synth test
|
2023-03-20 13:58:35 -04:00 |
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spi
|
reset pins and test clock
|
2023-05-10 14:35:57 -04:00 |
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waveform
|
reset pins and test clock
|
2023-05-10 14:35:57 -04:00 |
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Makefile
|
pass yosys
|
2023-03-15 17:08:55 -04:00 |
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common.makefile
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reset pins and test clock
|
2023-05-10 14:35:57 -04:00 |
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testbench.hpp
|
simulate waveform.v
|
2023-03-15 06:24:28 +00:00 |
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util.hpp
|
test and simulate spi_switch
|
2023-03-14 15:42:41 +00:00 |
Peter McGoron
67b07516cf