82 lines
1.7 KiB
Verilog
82 lines
1.7 KiB
Verilog
module bram_interface_sim #(
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parameter WORD_WID = 24,
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parameter WORD_AMNT_WID = 11,
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parameter [WORD_AMNT_WID-1:0] WORD_AMNT = 2047,
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parameter RAM_WID = 32,
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parameter RAM_WORD_WID = 16,
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parameter RAM_REAL_START = 32'h12340,
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parameter RAM_CNTR_LEN = 12,
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parameter TOTAL_RAM_WORD_MINUS_ONE = 4095,
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parameter DELAY_CNTR_LEN = 8,
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parameter DELAY_TOTAL = 12,
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parameter RAM_WORD_INCR = 2
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) (
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input clk,
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/* autoapproach interface */
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output [WORD_WID-1:0] word,
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input word_next,
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output word_last,
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output word_ok,
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input word_rst,
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/* User interface */
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input refresh_start,
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input [RAM_WID-1:0] start_addr,
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output refresh_finished,
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input[RAM_WORD_WID-1:0] backing_store [TOTAL_RAM_WORD_MINUS_ONE:0]
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);
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wire [RAM_WID-1:0] ram_dma_addr;
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wire [RAM_WORD_WID-1:0] ram_word;
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wire ram_read;
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wire ram_valid;
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dma_sim #(
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.RAM_WID(RAM_WID),
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.RAM_WORD_WID(RAM_WORD_WID),
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.RAM_REAL_START(RAM_REAL_START),
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.RAM_CNTR_LEN(RAM_CNTR_LEN),
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.TOTAL_RAM_WORD_MINUS_ONE(TOTAL_RAM_WORD_MINUS_ONE),
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.DELAY_CNTR_LEN(DELAY_CNTR_LEN),
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.DELAY_TOTAL(DELAY_TOTAL)
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) dma_sim (
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.clk(clk),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid),
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.backing_store(backing_store)
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);
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bram_interface #(
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.WORD_WID(WORD_WID),
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.WORD_AMNT_WID(WORD_AMNT_WID),
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.WORD_AMNT(WORD_AMNT),
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.RAM_WID(RAM_WID),
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.RAM_WORD_WID(RAM_WORD_WID),
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.RAM_WORD_INCR(RAM_WORD_INCR)
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) bram_interface (
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.clk(clk),
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.word(word),
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.word_next(word_next),
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.word_last(word_last),
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.word_ok(word_ok),
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.word_rst(word_rst),
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.refresh_start(refresh_start),
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.start_addr(start_addr),
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.refresh_finished(refresh_finished),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid)
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);
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initial begin
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$dumpfile("bram.fst");
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$dumpvars();
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end
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endmodule
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