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Makefile
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pass yosys
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2023-03-15 17:08:55 -04:00 |
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adc_sim.v
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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boothmul.v.m4
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change control_loop to m4 scripts, add common makefile
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2023-03-15 18:30:08 +00:00 |
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boothmul_sim.cpp
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import updated boothmul
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2022-11-11 22:14:50 -05:00 |
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control_loop.v.m4
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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control_loop_cmds.h.m4
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add control_loop_cmds header generators
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2023-03-15 18:30:30 +00:00 |
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control_loop_cmds.m4
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change control_loop to m4 scripts, add common makefile
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2023-03-15 18:30:08 +00:00 |
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control_loop_cmds.vh.m4
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add control_loop_cmds header generators
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2023-03-15 18:30:30 +00:00 |
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control_loop_math.v.m4
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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control_loop_math_implementation.cpp
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Rewrite control_loop_math and simulate
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2022-11-13 18:03:55 -05:00 |
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control_loop_math_implementation.h
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Rewrite control_loop_math and simulate
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2022-11-13 18:03:55 -05:00 |
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control_loop_math_sim.cpp
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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control_loop_sim.cpp
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Added more comments to file
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2023-01-29 16:31:15 -05:00 |
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control_loop_sim_top.v
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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dac_sim.v
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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intro.md
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integrate control_loop_math into control_loop
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2022-11-17 19:07:21 -05:00 |
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intsat.v
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add everything im working on
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2022-09-16 18:01:34 -04:00 |
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intsat_sim.cpp
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move simulators to the same directory of the simulated core
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2022-10-17 00:45:19 -04:00 |
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intsat_testbench.v
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Add files via upload
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2023-01-30 14:09:49 -05:00 |
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sign_extend.v
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Rewrite control_loop_math and simulate
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2022-11-13 18:03:55 -05:00 |
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yosys_test.sh
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add yosys synth test for control loop
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2023-03-20 13:57:42 -04:00 |
Peter McGoron
15b8fcbe7e