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Free and open source SoC for Scanning Probe Microscopy
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Verilog 44.7%
Python 23.4%
C++ 11.8%
Tcl 7.6%
M4 5.7%
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Peter McGoron 9d35754dab add makefile; condense LiteX CSRs 2022-07-12 13:29:26 -04:00
A7-constraints.xdc import constraints 2022-07-11 12:02:16 -04:00
Makefile add makefile; condense LiteX CSRs 2022-07-12 13:29:26 -04:00
soc.py add makefile; condense LiteX CSRs 2022-07-12 13:29:26 -04:00