59 lines
1.4 KiB
Verilog
59 lines
1.4 KiB
Verilog
/* YOSYS has a difficult time infering single port BRAM. It can infer
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* double-port block ram, however. This module is written as a double
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* port block ram, even though both clocks will end up being the same.
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* TODO:
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* "empty" and "full" status indiciators for simulation
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* https://stackoverflow.com/questions/62703942/trouble-getting-yosys-to-infer-block-ram-array-rather-than-using-logic-cells-v
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* The answer by "TinLethax" infers a BRAM.
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*/
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module ram_fifo_dual_port #(
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parameter DAT_WID = 24,
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parameter FIFO_DEPTH = 1500,
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parameter FIFO_DEPTH_WID = 11
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) (
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input RCLK,
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input WCLK,
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input rst,
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input read_enable,
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input write_enable,
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input signed [DAT_WID-1:0] write_dat,
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output reg signed [DAT_WID-1:0] read_dat
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);
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reg [DAT_WID-1:0] memory [FIFO_DEPTH-1:0];
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initial memory[0] = 24'b0;
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/* Read domain */
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reg [FIFO_DEPTH_WID-1:0] read_ptr = 0;
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always @ (posedge RCLK) begin
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if (rst) begin
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read_ptr <= 0;
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end else if (read_enable) begin
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read_dat <= memory[read_ptr];
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if (read_ptr == FIFO_DEPTH-1)
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read_ptr <= 0;
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else
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read_ptr <= read_ptr + 1;
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end
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end
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/* Write domain */
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reg [FIFO_DEPTH_WID-1:0] write_ptr = 0;
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always @ (posedge WCLK) begin
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if (rst) begin
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write_ptr <= 0;
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end else if (write_enable) begin
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memory[write_ptr] <= write_dat;
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if (write_ptr == FIFO_DEPTH-1)
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write_ptr <= 0;
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else
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write_ptr <= write_ptr + 1;
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end
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end
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endmodule
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