29 lines
526 B
Verilog
29 lines
526 B
Verilog
module top (
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input clk,
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input [1:0] btn,
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input ck_io0,
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input ck_io1,
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input ck_io2,
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input ck_io3,
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output ck_io4,
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output ck_io5,
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output ck_io6,
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output ck_io7,
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);
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wire bufg;
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BUFG bufgctrl (
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.I(clk),
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.O(bufg)
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);
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ram_fifo #(.DAT_WID(4), .FIFO_DEPTH(65535/2), .FIFO_DEPTH_WID(16) ) rf (
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.clk(bufg),
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.rst(0),
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.read_enable(btn[0]),
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.write_enable(btn[1]),
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.write_dat({ck_io0,ck_io1,ck_io2,ck_io3}),
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.read_dat({ck_io4,ck_io5,ck_io6,ck_io7})
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);
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endmodule
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