375 lines
10 KiB
Plaintext
375 lines
10 KiB
Plaintext
m4_changequote(`⟨', `⟩')
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m4_changecom(⟨/*⟩, ⟨*/⟩)
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m4_define(generate_macro, ⟨m4_define(M4_$1, $2)⟩)
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m4_include(../control_loop/control_loop_cmds.m4)
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/* Since yosys only allows for standard Verilog (no system verilog),
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* arrays (which would make everything much cleaner) cannot be used.
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* A preprocessor is used instead, and M4 is used because it is much
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* cleaner than the Verilog preprocessor (which is bad).
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* TODO: individual RST pins
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*/
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/*********************************************************/
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/********************** M4 macros ************************/
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/*********************************************************/
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/* This macro is used in the module declaration.
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* The first argument is the number of wires the select switch must
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* support (2 for most DACs, 3 for the control loop DAC).
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* The second argument is the DAC number.
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*/
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m4_define(m4_dac_wires, ⟨
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input [$1-1:0] dac_sel_$2,
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output dac_finished_$2,
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input dac_arm_$2,
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output [DAC_WID-1:0] from_dac_$2,
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input [DAC_WID-1:0] to_dac_$2,
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input wf_arm_$2,
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input wf_halt_on_finish_$2,
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output wf_finished_$2,
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input [WF_TIMER_WID-1:0] wf_time_to_wait_$2,
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input wf_refresh_start_$2,
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input [WF_RAM_WID-1:0] wf_start_addr_$2,
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output wf_refresh_finished_$2,
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output wf_running_$2,
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output [WF_RAM_WID-1:0] wf_ram_dma_addr_$2,
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input [WF_RAM_WORD_WID-1:0] wf_ram_word_$2,
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output wf_ram_read_$2,
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input wf_ram_valid_$2
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⟩)
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/* Same thing but for ADCs */
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m4_define(m4_adc_wires, ⟨
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input [$3-1:0] adc_sel_$2,
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output adc_finished_$2,
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input adc_arm_$2,
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output [$1-1:0] from_adc_$2
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⟩)
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/* This is used in the body of the module. It declares the interconnect
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* for each DAC. The first argument is the amount of switch ports the
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* DAC requires (2 for most DACs, 3 for the control loop DAC). The
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* second argument is the DAC number.
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*/
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m4_define(m4_dac_switch, ⟨
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wire [$1-1:0] mosi_port_$2;
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wire [$1-1:0] miso_port_$2;
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wire [$1-1:0] sck_port_$2;
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wire [$1-1:0] ss_L_port_$2;
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spi_switch #(
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.PORTS($1)
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) switch_$2 (
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.select(dac_sel_$2),
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.mosi(dac_mosi[$2]),
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.miso(dac_miso[$2]),
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.sck(dac_sck[$2]),
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.ss_L(dac_ss_L[$2]),
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.mosi_ports(mosi_port_$2),
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.miso_ports(miso_port_$2),
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.sck_ports(sck_port_$2),
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.ss_L_ports(ss_L_port_$2)
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);
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spi_master_ss #(
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.WID(DAC_WID),
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.WID_LEN(DAC_WID_SIZ),
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.CYCLE_HALF_WAIT(DAC_CYCLE_HALF_WAIT),
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.TIMER_LEN(DAC_CYCLE_HALF_WAIT_SIZ),
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.POLARITY(DAC_POLARITY),
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.PHASE(DAC_PHASE),
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.SS_WAIT(DAC_SS_WAIT),
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.SS_WAIT_TIMER_LEN(DAC_SS_WAIT_SIZ)
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) dac_master_$2 (
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.clk(clk),
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.rst_L(rst_L),
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.mosi(mosi_port_$2[0]),
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.miso(miso_port_$2[0]),
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.sck_wire(sck_port_$2[0]),
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.ss_L(ss_L_port_$2[0]),
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.finished(dac_finished_$2),
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.arm(dac_arm_$2),
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.from_slave(from_dac_$2),
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.to_slave(to_dac_$2)
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);
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waveform #(
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.DAC_WID(DAC_WID),
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.DAC_WID_SIZ(DAC_WID_SIZ),
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.DAC_POLARITY(DAC_POLARITY),
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.DAC_PHASE(DAC_PHASE),
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.DAC_CYCLE_HALF_WAIT(DAC_CYCLE_HALF_WAIT),
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.DAC_CYCLE_HALF_WAIT_SIZ(DAC_CYCLE_HALF_WAIT_SIZ),
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.DAC_SS_WAIT(DAC_SS_WAIT),
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.DAC_SS_WAIT_SIZ(DAC_SS_WAIT_SIZ),
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.TIMER_WID(WF_TIMER_WID),
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.WORD_WID(WF_WORD_WID),
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.WORD_AMNT_WID(WF_WORD_AMNT_WID),
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.WORD_AMNT(WF_WORD_AMNT),
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.RAM_WID(WF_RAM_WID),
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.RAM_WORD_WID(WF_RAM_WORD_WID),
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.RAM_WORD_INCR(WF_RAM_WORD_INCR)
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) waveform_$2 (
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.clk(clk),
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.arm(wf_arm_$2),
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.halt_on_finish(wf_halt_on_finish_$2),
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.running(wf_running_$2),
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.finished(wf_finished_$2),
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.time_to_wait(wf_time_to_wait_$2),
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.refresh_start(wf_refresh_start_$2),
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.start_addr(wf_start_addr_$2),
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.refresh_finished(wf_refresh_finished_$2),
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.ram_dma_addr(wf_ram_dma_addr_$2),
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.ram_word(wf_ram_word_$2),
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.ram_read(wf_ram_read_$2),
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.ram_valid(wf_ram_valid_$2),
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.mosi(mosi_port_$2[1]),
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.sck(sck_port_$2[1]),
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.ss_L(ss_L_port_$2[1])
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)
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⟩)
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/* Same thing but for ADCs */
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m4_define(m4_adc_switch, ⟨
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wire adc_mosi_unused_output_$2;
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wire [$3-1:0] adc_mosi_port_$2; /* Unused! */
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wire [$3-1:0] adc_sdo_port_$2;
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wire [$3-1:0] adc_sck_port_$2;
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wire [$3-1:0] adc_conv_L_port_$2;
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spi_switch #(
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.PORTS($3)
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) adc_switch_$2 (
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.select(adc_sel_$2),
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.mosi(adc_mosi_unused_output_$2),
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.miso(adc_sdo[$2]),
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.sck(adc_sck[$2]),
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.ss_L(adc_conv_L[$2]),
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.mosi_ports(adc_mosi_port_$2),
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.miso_ports(adc_sdo_port_$2),
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.sck_ports(adc_sck_port_$2),
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.ss_L_ports(adc_conv_L_port_$2)
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);
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spi_master_ss_no_write #(
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.WID($1),
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.WID_LEN(ADC_WID_SIZ),
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.CYCLE_HALF_WAIT(ADC_CYCLE_HALF_WAIT),
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.TIMER_LEN(ADC_CYCLE_HALF_WAIT_SIZ),
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.SS_WAIT(ADC_CONV_WAIT),
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.SS_WAIT_TIMER_LEN(ADC_CONV_WAIT_SIZ),
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.POLARITY(ADC_POLARITY),
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.PHASE(ADC_PHASE)
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) adc_master_$2 (
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.clk(clk),
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.rst_L(rst_L),
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.miso(adc_sdo_port_$2[0]),
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.sck_wire(adc_sck_port_$2[0]),
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.ss_L(adc_conv_L_port_$2[0]),
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.finished(adc_finished_$2),
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.arm(adc_arm_$2),
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.from_slave(from_adc_$2)
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);
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/* 2nd option for each ADC is the non-converting option.
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* This is used to flush output from reset ADCs.
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* TODO: Lower power consumption by having SCK low while converter is
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* not running? May require change to spi code.
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*/
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assign adc_sdo_port[1] = adc_sdo_port[0];
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assign adc_sck_port[1] = adc_sck_port[0];
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assign adc_conv_L_port[1] = 1;
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⟩)
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/*********************************************************/
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/*********************** Verilog *************************/
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/*********************************************************/
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module base #(
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parameter DAC_PORTS = 2,
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m4_define(DAC_PORTS_CONTROL_LOOP, (DAC_PORTS + 1))
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parameter DAC_NUM = 8,
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parameter DAC_WID = 24,
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parameter DAC_DATA_WID = 20,
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parameter DAC_WID_SIZ = 5,
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parameter DAC_POLARITY = 0,
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parameter DAC_PHASE = 1,
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parameter DAC_CYCLE_HALF_WAIT = 10,
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parameter DAC_CYCLE_HALF_WAIT_SIZ = 4,
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parameter DAC_SS_WAIT = 5,
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parameter DAC_SS_WAIT_SIZ = 3,
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parameter WF_TIMER_WID = 32,
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parameter WF_WORD_WID = 20,
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parameter WF_WORD_AMNT_WID = 11,
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parameter [WF_WORD_AMNT_WID-1:0] WF_WORD_AMNT = 2047,
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parameter WF_RAM_WID = 32,
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parameter WF_RAM_WORD_WID = 16,
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parameter WF_RAM_WORD_INCR = 2,
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parameter ADC_PORTS = 2,
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m4_define(ADC_PORTS_CONTROL_LOOP, (ADC_PORTS + 1))
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parameter ADC_NUM = 8,
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/* Three types of ADC. For now assume that their electronics
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* are similar enough, just need different numbers for the width.
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*/
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parameter ADC_TYPE1_WID = 18,
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parameter ADC_TYPE2_WID = 16,
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parameter ADC_TYPE3_WID = 24,
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parameter ADC_WID_SIZ = 5,
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parameter ADC_CYCLE_HALF_WAIT = 5,
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parameter ADC_CYCLE_HALF_WAIT_SIZ = 3,
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parameter ADC_POLARITY = 1,
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parameter ADC_PHASE = 0,
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/* The ADC takes maximum 527 ns to capture a value.
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* The clock ticks at 10 ns. Change for different clocks!
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*/
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parameter ADC_CONV_WAIT = 53,
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parameter ADC_CONV_WAIT_SIZ = 6,
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parameter CL_CONSTS_WHOLE = 21,
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parameter CL_CONSTS_FRAC = 43,
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parameter CL_CONSTS_SIZ = 7,
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parameter CL_DELAY_WID = 16,
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m4_define(CL_CONSTS_WID, (CL_CONSTS_WHOLE + CL_CONSTS_FRAC))
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m4_define(CL_DATA_WID, CL_CONSTS_WID)
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parameter CL_READ_DAC_DELAY = 5,
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parameter CL_CYCLE_COUNT_WID = 18
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) (
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input clk,
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input rst_L,
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output [11-1:0] set_low,
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output [DAC_NUM-1:0] dac_mosi,
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input [DAC_NUM-1:0] dac_miso,
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output [DAC_NUM-1:0] dac_sck,
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output [DAC_NUM-1:0] dac_ss_L,
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output [ADC_NUM-1:0] adc_conv,
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input [ADC_NUM-1:0] adc_sdo,
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output [ADC_NUM-1:0] adc_sck,
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m4_dac_wires(DAC_PORTS_CONTROL_LOOP, 0),
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m4_dac_wires(DAC_PORTS, 1),
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m4_dac_wires(DAC_PORTS, 2),
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m4_dac_wires(DAC_PORTS, 3),
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m4_dac_wires(DAC_PORTS, 4),
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m4_dac_wires(DAC_PORTS, 5),
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m4_dac_wires(DAC_PORTS, 6),
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m4_dac_wires(DAC_PORTS, 7),
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m4_adc_wires(ADC_TYPE1_WID, 0, ADC_PORTS_CONTROL_LOOP),
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m4_adc_wires(ADC_TYPE1_WID, 1, ADC_PORTS),
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m4_adc_wires(ADC_TYPE1_WID, 2, ADC_PORTS),
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m4_adc_wires(ADC_TYPE1_WID, 3, ADC_PORTS),
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m4_adc_wires(ADC_TYPE1_WID, 4, ADC_PORTS),
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m4_adc_wires(ADC_TYPE1_WID, 5, ADC_PORTS),
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m4_adc_wires(ADC_TYPE1_WID, 6, ADC_PORTS),
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m4_adc_wires(ADC_TYPE1_WID, 7, ADC_PORTS),
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output cl_in_loop,
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input [M4_CONTROL_LOOP_CMD_WIDTH-1:0] cl_cmd,
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input [CL_DATA_WID-1:0] cl_word_in,
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output reg [CL_DATA_WID-1:0] cl_word_out,
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input cl_start_cmd,
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output reg cl_finish_cmd
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,output reg test_clock
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);
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assign set_low = 0;
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wire [ADC_NUM-1:0] adc_conv_L;
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assign adc_conv = ~adc_conv_L;
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m4_dac_switch(DAC_PORTS_CONTROL_LOOP, 0);
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m4_dac_switch(DAC_PORTS, 1);
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m4_dac_switch(DAC_PORTS, 2);
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m4_dac_switch(DAC_PORTS, 3);
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m4_dac_switch(DAC_PORTS, 4);
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m4_dac_switch(DAC_PORTS, 5);
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m4_dac_switch(DAC_PORTS, 6);
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m4_dac_switch(DAC_PORTS, 7);
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initial test_clock <= 0;
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`ifdef MAKE_TEST_CLOCK
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reg [8-1:0] counter = 0;
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always @ (posedge clk) begin
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if (!rst_L) begin
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counter <= 0;
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test_clock <= 0;
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end else begin
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if (counter >= 3) begin
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counter <= 0;
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test_clock <= !test_clock;
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end else begin
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counter <= counter + 1;
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end
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end
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end
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`else
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assign test_clock = 0;
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`endif
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m4_adc_switch(ADC_TYPE1_WID, 0, ADC_PORTS_CONTROL_LOOP);
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m4_adc_switch(ADC_TYPE1_WID, 1, ADC_PORTS);
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m4_adc_switch(ADC_TYPE1_WID, 2, ADC_PORTS);
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m4_adc_switch(ADC_TYPE1_WID, 3, ADC_PORTS);
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m4_adc_switch(ADC_TYPE1_WID, 4, ADC_PORTS);
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m4_adc_switch(ADC_TYPE1_WID, 5, ADC_PORTS);
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m4_adc_switch(ADC_TYPE1_WID, 6, ADC_PORTS);
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m4_adc_switch(ADC_TYPE1_WID, 7, ADC_PORTS);
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control_loop #(
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.ADC_WID(ADC_TYPE1_WID),
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.ADC_WID_SIZ(ADC_WID_SIZ),
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.ADC_CYCLE_HALF_WAIT(ADC_CYCLE_HALF_WAIT),
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.ADC_CYCLE_HALF_WAIT_SIZ(ADC_CYCLE_HALF_WAIT_SIZ),
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.ADC_POLARITY(ADC_POLARITY),
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.ADC_PHASE(ADC_PHASE),
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.ADC_CONV_WAIT(ADC_CONV_WAIT),
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.ADC_CONV_WAIT_SIZ(ADC_CONV_WAIT_SIZ),
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.CONSTS_WHOLE(CL_CONSTS_WHOLE),
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.CONSTS_FRAC(CL_CONSTS_FRAC),
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.CONSTS_SIZ(CL_CONSTS_SIZ),
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.DELAY_WID(CL_DELAY_WID),
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.READ_DAC_DELAY(CL_READ_DAC_DELAY),
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.CYCLE_COUNT_WID(CL_CYCLE_COUNT_WID),
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.DAC_WID(DAC_WID),
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.DAC_WID_SIZ(DAC_WID_SIZ),
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.DAC_DATA_WID(DAC_DATA_WID),
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.DAC_POLARITY(DAC_POLARITY),
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.DAC_PHASE(DAC_PHASE),
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.DAC_CYCLE_HALF_WAIT(DAC_CYCLE_HALF_WAIT),
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.DAC_CYCLE_HALF_WAIT_SIZ(DAC_CYCLE_HALF_WAIT_SIZ),
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.DAC_SS_WAIT(DAC_SS_WAIT),
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.DAC_SS_WAIT_SIZ(DAC_SS_WAIT_SIZ)
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) cl (
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.clk(clk),
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.rst_L(rst_L),
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.in_loop(cl_in_loop),
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.dac_mosi(mosi_port_0[2]),
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.dac_miso(miso_port_0[2]),
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.dac_ss_L(ss_L_port_0[2]),
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.dac_sck(sck_port_0[2]),
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.adc_miso(adc_sdo_port_0[2]),
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.adc_conv_L(adc_conv_L_port_0[2]),
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.adc_sck(adc_sck_port_0[2]),
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.cmd(cl_cmd),
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.word_in(cl_word_in),
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.word_out(cl_word_out),
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.start_cmd(cl_start_cmd),
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.finish_cmd(cl_finish_cmd)
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);
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endmodule
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